git.openwrt.org Git - openwrt/staging/rmilecki.git/blob

   1 From 6d15419acb9914041e90bc88044d87bbcdcfec00 Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Tue, 15 Dec 2020 16:42:41 +0100
   4 Subject: [PATCH] drm/vc4: hdmi: Use the connector state pixel rate for
   5  the PHY
   6
   7 The PHY initialisation parameters are not based on the pixel clock but
   8 the TMDS clock rate which can be the pixel clock in the standard case,
   9 but could be adjusted based on some parameters like the bits per color.
  10
  11 Since the TMDS clock rate is stored in our custom connector state
  12 already, let's reuse it from there instead of computing it again.
  13
  14 Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
  15 Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  16 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  17 ---
  18  drivers/gpu/drm/vc4/vc4_hdmi.c     |  2 +-
  19  drivers/gpu/drm/vc4/vc4_hdmi.h     | 11 +++++------
  20  drivers/gpu/drm/vc4/vc4_hdmi_phy.c |  8 +++++---
  21  3 files changed, 11 insertions(+), 10 deletions(-)
  22
  23 --- a/drivers/gpu/drm/vc4/vc4_hdmi.c
  24 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.c
  25 @@ -761,7 +761,7 @@ static void vc4_hdmi_encoder_pre_crtc_co
  26         }
  27
  28         if (vc4_hdmi->variant->phy_init)
  29 -               vc4_hdmi->variant->phy_init(vc4_hdmi, mode);
  30 +               vc4_hdmi->variant->phy_init(vc4_hdmi, vc4_conn_state);
  31
  32         HDMI_WRITE(HDMI_SCHEDULER_CONTROL,
  33                    HDMI_READ(HDMI_SCHEDULER_CONTROL) |
  34 --- a/drivers/gpu/drm/vc4/vc4_hdmi.h
  35 +++ b/drivers/gpu/drm/vc4/vc4_hdmi.h
  36 @@ -21,10 +21,9 @@ to_vc4_hdmi_encoder(struct drm_encoder *
  37         return container_of(encoder, struct vc4_hdmi_encoder, base.base);
  38  }
  39
  40 -struct drm_display_mode;
  41 -
  42  struct vc4_hdmi;
  43  struct vc4_hdmi_register;
  44 +struct vc4_hdmi_connector_state;
  45
  46  enum vc4_hdmi_phy_channel {
  47         PHY_LANE_0 = 0,
  48 @@ -77,9 +76,9 @@ struct vc4_hdmi_variant {
  49         void (*set_timings)(struct vc4_hdmi *vc4_hdmi,
  50                             struct drm_display_mode *mode);
  51
  52 -       /* Callback to initialize the PHY according to the mode */
  53 +       /* Callback to initialize the PHY according to the connector state */
  54         void (*phy_init)(struct vc4_hdmi *vc4_hdmi,
  55 -                        struct drm_display_mode *mode);
  56 +                        struct vc4_hdmi_connector_state *vc4_conn_state);
  57
  58         /* Callback to disable the PHY */
  59         void (*phy_disable)(struct vc4_hdmi *vc4_hdmi);
  60 @@ -199,13 +198,13 @@ conn_state_to_vc4_hdmi_conn_state(struct
  61  }
  62
  63  void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
  64 -                      struct drm_display_mode *mode);
  65 +                      struct vc4_hdmi_connector_state *vc4_conn_state);
  66  void vc4_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
  67  void vc4_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);
  68  void vc4_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);
  69
  70  void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
  71 -                      struct drm_display_mode *mode);
  72 +                      struct vc4_hdmi_connector_state *vc4_conn_state);
  73  void vc5_hdmi_phy_disable(struct vc4_hdmi *vc4_hdmi);
  74  void vc5_hdmi_phy_rng_enable(struct vc4_hdmi *vc4_hdmi);
  75  void vc5_hdmi_phy_rng_disable(struct vc4_hdmi *vc4_hdmi);
  76 --- a/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
  77 +++ b/drivers/gpu/drm/vc4/vc4_hdmi_phy.c
  78 @@ -127,7 +127,8 @@
  79
  80  #define OSCILLATOR_FREQUENCY   54000000
  81
  82 -void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_display_mode *mode)
  83 +void vc4_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
  84 +                      struct vc4_hdmi_connector_state *conn_state)
  85  {
  86         /* PHY should be in reset, like
  87          * vc4_hdmi_encoder_disable() does.
  88 @@ -339,11 +340,12 @@ static void vc5_hdmi_reset_phy(struct vc
  89         HDMI_WRITE(HDMI_TX_PHY_POWERDOWN_CTL, BIT(10));
  90  }
  91
  92 -void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi, struct drm_display_mode *mode)
  93 +void vc5_hdmi_phy_init(struct vc4_hdmi *vc4_hdmi,
  94 +                      struct vc4_hdmi_connector_state *conn_state)
  95  {
  96         const struct phy_lane_settings *chan0_settings, *chan1_settings, *chan2_settings, *clock_settings;
  97         const struct vc4_hdmi_variant *variant = vc4_hdmi->variant;
  98 -       unsigned long long pixel_freq = mode->clock * 1000;
  99 +       unsigned long long pixel_freq = conn_state->pixel_rate;
 100         unsigned long long vco_freq;
 101         unsigned char word_sel;
 102         u8 vco_sel, vco_div;