git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 7fe646b726b66c16f731e36e95d7eda9f182ba4d Mon Sep 17 00:00:00 2001
   2 From: Maxime Ripard <maxime@cerno.tech>
   3 Date: Thu, 3 Dec 2020 14:25:38 +0100
   4 Subject: [PATCH] drm/vc4: dsi: Use snprintf for the PHY clocks instead
   5  of an array
   6
   7 Commit dc0bf36401e891c853e0a25baeb4e0b4e6f3626d upstream.
   8
   9 The DSI clocks setup function has been using an array to store the clock
  10 name of either the DSI0 or DSI1 blocks, using the port ID to choose the
  11 proper one.
  12
  13 Let's switch to an snprintf call to do the same thing and simplify the
  14 array a bit.
  15
  16 Reviewed-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  17 Signed-off-by: Maxime Ripard <maxime@cerno.tech>
  18 Link: https://patchwork.freedesktop.org/patch/msgid/20201203132543.861591-4-maxime@cerno.tech
  19 ---
  20  drivers/gpu/drm/vc4/vc4_dsi.c | 17 +++++++++--------
  21  1 file changed, 9 insertions(+), 8 deletions(-)
  22
  23 --- a/drivers/gpu/drm/vc4/vc4_dsi.c
  24 +++ b/drivers/gpu/drm/vc4/vc4_dsi.c
  25 @@ -1390,12 +1390,12 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *
  26         struct device *dev = &dsi->pdev->dev;
  27         const char *parent_name = __clk_get_name(dsi->pll_phy_clock);
  28         static const struct {
  29 -               const char *dsi0_name, *dsi1_name;
  30 +               const char *name;
  31                 int div;
  32         } phy_clocks[] = {
  33 -               { "dsi0_byte", "dsi1_byte", 8 },
  34 -               { "dsi0_ddr2", "dsi1_ddr2", 4 },
  35 -               { "dsi0_ddr", "dsi1_ddr", 2 },
  36 +               { "byte", 8 },
  37 +               { "ddr2", 4 },
  38 +               { "ddr", 2 },
  39         };
  40         int i;
  41
  42 @@ -1411,8 +1411,12 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *
  43         for (i = 0; i < ARRAY_SIZE(phy_clocks); i++) {
  44                 struct clk_fixed_factor *fix = &dsi->phy_clocks[i];
  45                 struct clk_init_data init;
  46 +               char clk_name[16];
  47                 int ret;
  48
  49 +               snprintf(clk_name, sizeof(clk_name),
  50 +                        "dsi%u_%s", dsi->port, phy_clocks[i].name);
  51 +
  52                 /* We just use core fixed factor clock ops for the PHY
  53                  * clocks.  The clocks are actually gated by the
  54                  * PHY_AFEC0_DDRCLK_EN bits, which we should be
  55 @@ -1429,10 +1433,7 @@ vc4_dsi_init_phy_clocks(struct vc4_dsi *
  56                 memset(&init, 0, sizeof(init));
  57                 init.parent_names = &parent_name;
  58                 init.num_parents = 1;
  59 -               if (dsi->port == 1)
  60 -                       init.name = phy_clocks[i].dsi1_name;
  61 -               else
  62 -                       init.name = phy_clocks[i].dsi0_name;
  63 +               init.name = clk_name;
  64                 init.ops = &clk_fixed_factor_ops;
  65
  66                 ret = devm_clk_hw_register(dev, &fix->hw);