git.openwrt.org Git - openwrt/staging/wigyori.git/blob

   1 From 5f5997322584b6257543d4d103f81484b8006d84 Mon Sep 17 00:00:00 2001
   2 From: Lorenzo Bianconi <lorenzo@kernel.org>
   3 Date: Fri, 17 Nov 2023 17:42:59 +0100
   4 Subject: [PATCH 4/5] net: ethernet: mtk_wed: add support for devices with more
   5  than 4GB of dram
   6
   7 Introduce WED offloading support for boards with more than 4GB of
   8 memory.
   9
  10 Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
  11 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
  12 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  13 Link: https://lore.kernel.org/r/1c7efdf5d384ea7af3c0209723e40b2ee0f956bf.1700239272.git.lorenzo@kernel.org
  14 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  15 ---
  16  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
  17  drivers/net/ethernet/mediatek/mtk_wed.c     | 8 +++++---
  18  drivers/net/ethernet/mediatek/mtk_wed_wo.c  | 3 ++-
  19  3 files changed, 11 insertions(+), 5 deletions(-)
  20
  21 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  22 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  23 @@ -1158,15 +1158,18 @@ static int mtk_init_fq_dma(struct mtk_et
  24         phy_ring_tail = eth->phy_scratch_ring + soc->tx.desc_size * (cnt - 1);
  25
  26         for (i = 0; i < cnt; i++) {
  27 +               dma_addr_t addr = dma_addr + i * MTK_QDMA_PAGE_SIZE;
  28                 struct mtk_tx_dma_v2 *txd;
  29
  30                 txd = eth->scratch_ring + i * soc->tx.desc_size;
  31 -               txd->txd1 = dma_addr + i * MTK_QDMA_PAGE_SIZE;
  32 +               txd->txd1 = addr;
  33                 if (i < cnt - 1)
  34                         txd->txd2 = eth->phy_scratch_ring +
  35                                     (i + 1) * soc->tx.desc_size;
  36
  37                 txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
  38 +               if (MTK_HAS_CAPS(soc->caps, MTK_36BIT_DMA))
  39 +                       txd->txd3 |= TX_DMA_PREP_ADDR64(addr);
  40                 txd->txd4 = 0;
  41                 if (mtk_is_netsys_v2_or_greater(eth)) {
  42                         txd->txd5 = 0;
  43 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
  44 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
  45 @@ -691,10 +691,11 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
  46
  47                 for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {
  48                         struct mtk_wdma_desc *desc = desc_ptr;
  49 +                       u32 ctrl;
  50
  51                         desc->buf0 = cpu_to_le32(buf_phys);
  52                         if (!mtk_wed_is_v3_or_greater(dev->hw)) {
  53 -                               u32 txd_size, ctrl;
  54 +                               u32 txd_size;
  55
  56                                 txd_size = dev->wlan.init_buf(buf, buf_phys,
  57                                                               token++);
  58 @@ -708,11 +709,11 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
  59                                         ctrl |= MTK_WDMA_DESC_CTRL_LAST_SEG0 |
  60                                                 FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2,
  61                                                            MTK_WED_BUF_SIZE - txd_size);
  62 -                               desc->ctrl = cpu_to_le32(ctrl);
  63                                 desc->info = 0;
  64                         } else {
  65 -                               desc->ctrl = cpu_to_le32(token << 16);
  66 +                               ctrl = token << 16 | TX_DMA_PREP_ADDR64(buf_phys);
  67                         }
  68 +                       desc->ctrl = cpu_to_le32(ctrl);
  69
  70                         desc_ptr += desc_size;
  71                         buf += MTK_WED_BUF_SIZE;
  72 @@ -811,6 +812,7 @@ mtk_wed_hwrro_buffer_alloc(struct mtk_we
  73                 buf_phys = page_phys;
  74                 for (s = 0; s < MTK_WED_RX_BUF_PER_PAGE; s++) {
  75                         desc->buf0 = cpu_to_le32(buf_phys);
  76 +                       desc->token = cpu_to_le32(RX_DMA_PREP_ADDR64(buf_phys));
  77                         buf_phys += MTK_WED_PAGE_BUF_SIZE;
  78                         desc++;
  79                 }
  80 --- a/drivers/net/ethernet/mediatek/mtk_wed_wo.c
  81 +++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.c
  82 @@ -142,7 +142,8 @@ mtk_wed_wo_queue_refill(struct mtk_wed_w
  83                 dma_addr_t addr;
  84                 void *buf;
  85
  86 -               buf = page_frag_alloc(&q->cache, q->buf_size, GFP_ATOMIC);
  87 +               buf = page_frag_alloc(&q->cache, q->buf_size,
  88 +                                     GFP_ATOMIC | GFP_DMA32);
  89                 if (!buf)
  90                         break;
  91