git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From 0a9ec38c47c1ca4528aa058e2b9ea61901a7e632 Mon Sep 17 00:00:00 2001
   2 From: Komal Bajaj <quic_kbajaj@quicinc.com>
   3 Date: Tue, 1 Aug 2023 12:10:25 +0530
   4 Subject: [PATCH] nvmem: sec-qfprom: Add Qualcomm secure QFPROM support
   5
   6 For some of the Qualcomm SoC's, it is possible that
   7 some of the fuse regions or entire qfprom region is
   8 protected from non-secure access. In such situations,
   9 the OS will have to use secure calls to read the region.
  10 With that motivation, add secure qfprom driver.
  11
  12 Signed-off-by: Komal Bajaj <quic_kbajaj@quicinc.com>
  13 Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
  14 ---
  15  drivers/nvmem/Kconfig      | 13 ++++++
  16  drivers/nvmem/Makefile     |  2 +
  17  drivers/nvmem/sec-qfprom.c | 96 ++++++++++++++++++++++++++++++++++++++
  18  3 files changed, 111 insertions(+)
  19  create mode 100644 drivers/nvmem/sec-qfprom.c
  20
  21 --- a/drivers/nvmem/Kconfig
  22 +++ b/drivers/nvmem/Kconfig
  23 @@ -226,6 +226,19 @@ config NVMEM_QCOM_QFPROM
  24           This driver can also be built as a module. If so, the module
  25           will be called nvmem_qfprom.
  26
  27 +config NVMEM_QCOM_SEC_QFPROM
  28 +        tristate "QCOM SECURE QFPROM Support"
  29 +        depends on ARCH_QCOM || COMPILE_TEST
  30 +        depends on HAS_IOMEM
  31 +        depends on OF
  32 +        select QCOM_SCM
  33 +        help
  34 +          Say y here to enable secure QFPROM support. The secure QFPROM provides access
  35 +          functions for QFPROM data to rest of the drivers via nvmem interface.
  36 +
  37 +          This driver can also be built as a module. If so, the module will be called
  38 +          nvmem_sec_qfprom.
  39 +
  40  config NVMEM_RAVE_SP_EEPROM
  41         tristate "Rave SP EEPROM Support"
  42         depends on RAVE_SP_CORE
  43 --- a/drivers/nvmem/Makefile
  44 +++ b/drivers/nvmem/Makefile
  45 @@ -46,6 +46,8 @@ obj-$(CONFIG_NVMEM_NINTENDO_OTP)      += nvme
  46  nvmem-nintendo-otp-y                   := nintendo-otp.o
  47  obj-$(CONFIG_NVMEM_QCOM_QFPROM)                += nvmem_qfprom.o
  48  nvmem_qfprom-y                         := qfprom.o
  49 +obj-$(CONFIG_NVMEM_QCOM_SEC_QFPROM)    += nvmem_sec_qfprom.o
  50 +nvmem_sec_qfprom-y                     := sec-qfprom.o
  51  obj-$(CONFIG_NVMEM_RAVE_SP_EEPROM)     += nvmem-rave-sp-eeprom.o
  52  nvmem-rave-sp-eeprom-y                 := rave-sp-eeprom.o
  53  obj-$(CONFIG_NVMEM_RMEM)               += nvmem-rmem.o
  54 --- /dev/null
  55 +++ b/drivers/nvmem/sec-qfprom.c
  56 @@ -0,0 +1,96 @@
  57 +// SPDX-License-Identifier: GPL-2.0-only
  58 +/*
  59 + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
  60 + */
  61 +
  62 +#include <linux/qcom_scm.h>
  63 +#include <linux/mod_devicetable.h>
  64 +#include <linux/nvmem-provider.h>
  65 +#include <linux/platform_device.h>
  66 +#include <linux/pm_runtime.h>
  67 +
  68 +/**
  69 + * struct sec_qfprom - structure holding secure qfprom attributes
  70 + *
  71 + * @base: starting physical address for secure qfprom corrected address space.
  72 + * @dev: qfprom device structure.
  73 + */
  74 +struct sec_qfprom {
  75 +       phys_addr_t base;
  76 +       struct device *dev;
  77 +};
  78 +
  79 +static int sec_qfprom_reg_read(void *context, unsigned int reg, void *_val, size_t bytes)
  80 +{
  81 +       struct sec_qfprom *priv = context;
  82 +       unsigned int i;
  83 +       u8 *val = _val;
  84 +       u32 read_val;
  85 +       u8 *tmp;
  86 +
  87 +       for (i = 0; i < bytes; i++, reg++) {
  88 +               if (i == 0 || reg % 4 == 0) {
  89 +                       if (qcom_scm_io_readl(priv->base + (reg & ~3), &read_val)) {
  90 +                               dev_err(priv->dev, "Couldn't access fuse register\n");
  91 +                               return -EINVAL;
  92 +                       }
  93 +                       tmp = (u8 *)&read_val;
  94 +               }
  95 +
  96 +               val[i] = tmp[reg & 3];
  97 +       }
  98 +
  99 +       return 0;
 100 +}
 101 +
 102 +static int sec_qfprom_probe(struct platform_device *pdev)
 103 +{
 104 +       struct nvmem_config econfig = {
 105 +               .name = "sec-qfprom",
 106 +               .stride = 1,
 107 +               .word_size = 1,
 108 +               .id = NVMEM_DEVID_AUTO,
 109 +               .reg_read = sec_qfprom_reg_read,
 110 +       };
 111 +       struct device *dev = &pdev->dev;
 112 +       struct nvmem_device *nvmem;
 113 +       struct sec_qfprom *priv;
 114 +       struct resource *res;
 115 +
 116 +       priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 117 +       if (!priv)
 118 +               return -ENOMEM;
 119 +
 120 +       res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 121 +       if (!res)
 122 +               return -EINVAL;
 123 +
 124 +       priv->base = res->start;
 125 +
 126 +       econfig.size = resource_size(res);
 127 +       econfig.dev = dev;
 128 +       econfig.priv = priv;
 129 +
 130 +       priv->dev = dev;
 131 +
 132 +       nvmem = devm_nvmem_register(dev, &econfig);
 133 +
 134 +       return PTR_ERR_OR_ZERO(nvmem);
 135 +}
 136 +
 137 +static const struct of_device_id sec_qfprom_of_match[] = {
 138 +       { .compatible = "qcom,sec-qfprom" },
 139 +       {/* sentinel */},
 140 +};
 141 +MODULE_DEVICE_TABLE(of, sec_qfprom_of_match);
 142 +
 143 +static struct platform_driver qfprom_driver = {
 144 +       .probe = sec_qfprom_probe,
 145 +       .driver = {
 146 +               .name = "qcom_sec_qfprom",
 147 +               .of_match_table = sec_qfprom_of_match,
 148 +       },
 149 +};
 150 +module_platform_driver(qfprom_driver);
 151 +MODULE_DESCRIPTION("Qualcomm Secure QFPROM driver");
 152 +MODULE_LICENSE("GPL");