git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From 9344f58d60a0a53ec39e7c5d75021843e859970f Mon Sep 17 00:00:00 2001
   2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
   3 Date: Fri, 29 Nov 2019 03:18:32 +0200
   4 Subject: [PATCH] arm64: dts: fsl: ls1028a: Disable eno3 and make swp5 the
   5  Felix CPU port
   6
   7 This patch returns to the switch port setup from BSP 0.2, where the
   8 switch only had a single Ethernet connection to the CPU, via a tagging
   9 interface. Choose eno2 for this purpose, as it has higher bandwidth and
  10 also supports TSN offloads.
  11
  12 The reason is that the switch is not able to do DSA tags on 2 CPU ports
  13 at the same time, and it is confusing to have so many ports with no
  14 clear indication which should be used for what (a "data" port and a
  15 "control" port).
  16
  17 We don't revert to the BSP 0.2 RCW configuration, however. The ENETC
  18 port 3 is still enabled in the RCW, however it is not probed by Linux by
  19 default, since the large majority of use cases will not need it. For
  20 those that do (like originating 802.1CB traffic from the CPU), it can be
  21 enabled back by simply reverting this device tree change.
  22
  23 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
  24 ---
  25  arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 6 ++++--
  26  1 file changed, 4 insertions(+), 2 deletions(-)
  27
  28 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
  29 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
  30 @@ -773,7 +773,7 @@
  31                                 #address-cells = <1>;
  32                                 #size-cells = <0>;
  33                         };
  34 -                       ethernet@0,2 {
  35 +                       enetc_port2: ethernet@0,2 {
  36                                 compatible = "fsl,enetc";
  37                                 reg = <0x000200 0 0 0 0>;
  38                                 fixed-link {
  39 @@ -812,6 +812,7 @@
  40                                         /* internal to-cpu ports */
  41                                         port@4 {
  42                                                 reg = <4>;
  43 +                                               ethernet = <&enetc_port2>;
  44                                                 phy-mode = "gmii";
  45
  46                                                 fixed-link {
  47 @@ -821,7 +822,6 @@
  48                                         };
  49                                         port@5 {
  50                                                 reg = <5>;
  51 -                                               ethernet = <&enetc_port3>;
  52                                                 phy-mode = "gmii";
  53
  54                                                 fixed-link {
  55 @@ -834,6 +834,8 @@
  56                         enetc_port3: ethernet@0,6 {
  57                                 compatible = "fsl,enetc";
  58                                 reg = <0x000600 0 0 0 0>;
  59 +                               status = "disabled";
  60 +
  61                                 fixed-link {
  62                                         speed = <1000>;
  63                                         full-duplex;