git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 8cfa2576d79f9379d167a8994f0fca935c07a8bc Mon Sep 17 00:00:00 2001
   2 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
   3 Date: Sat, 22 Jul 2023 21:32:49 +0100
   4 Subject: [PATCH 096/250] net: ethernet: mtk_eth_soc: remove incorrect PLL
   5  configuration
   6
   7 MT7623 GMAC0 attempts to configure the system clocking according to the
   8 required speed in the .mac_config callback for non-SGMII, non-baseX and
   9 non-TRGMII modes.
  10
  11 state->speed setting has never been reliable in the .mac_config
  12 callback - there are cases where this is not the link speed,
  13 particularly via ethtool paths, so this has always been unreliable (as
  14 detailed in phylink's documentation.)
  15
  16 There is the additional issue that mtk_gmac0_rgmii_adjust() will only
  17 be called if state->interface changes, which means it only configures
  18 the system clocking on the very first .mac_config call, which will be
  19 made when the network device is first brought up before any link is
  20 established.
  21
  22 Essentially, this code is incredibly buggy, and probably never worked.
  23
  24 Moreover, checking the in-kernel DT files, it seems no platform makes
  25 use of this code path.
  26
  27 Therefore, let's remove it, and disable interface modes for port 0 that
  28 are not SGMII, 1000base-X, 2500base-X or TRGMII on the MT7623.
  29
  30 Reviewed-by: Daniel Golle <daniel@makrotopia.org>
  31 Tested-by: Daniel Golle <daniel@makrotopia.org>
  32 Tested-by: Frank Wunderlich <frank-w@public-files.de>
  33 Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  34 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  35 ---
  36  drivers/net/ethernet/mediatek/mtk_eth_soc.c | 54 ++++++---------------
  37  drivers/net/ethernet/mediatek/mtk_eth_soc.h |  1 +
  38  2 files changed, 17 insertions(+), 38 deletions(-)
  39
  40 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  41 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  42 @@ -352,7 +352,7 @@ static int mt7621_gmac0_rgmii_adjust(str
  43  }
  44
  45  static void mtk_gmac0_rgmii_adjust(struct mtk_eth *eth,
  46 -                                  phy_interface_t interface, int speed)
  47 +                                  phy_interface_t interface)
  48  {
  49         u32 val;
  50         int ret;
  51 @@ -366,26 +366,7 @@ static void mtk_gmac0_rgmii_adjust(struc
  52                 return;
  53         }
  54
  55 -       val = (speed == SPEED_1000) ?
  56 -               INTF_MODE_RGMII_1000 : INTF_MODE_RGMII_10_100;
  57 -       mtk_w32(eth, val, INTF_MODE);
  58 -
  59 -       regmap_update_bits(eth->ethsys, ETHSYS_CLKCFG0,
  60 -                          ETHSYS_TRGMII_CLK_SEL362_5,
  61 -                          ETHSYS_TRGMII_CLK_SEL362_5);
  62 -
  63 -       val = (speed == SPEED_1000) ? 250000000 : 500000000;
  64 -       ret = clk_set_rate(eth->clks[MTK_CLK_TRGPLL], val);
  65 -       if (ret)
  66 -               dev_err(eth->dev, "Failed to set trgmii pll: %d\n", ret);
  67 -
  68 -       val = (speed == SPEED_1000) ?
  69 -               RCK_CTRL_RGMII_1000 : RCK_CTRL_RGMII_10_100;
  70 -       mtk_w32(eth, val, TRGMII_RCK_CTRL);
  71 -
  72 -       val = (speed == SPEED_1000) ?
  73 -               TCK_CTRL_RGMII_1000 : TCK_CTRL_RGMII_10_100;
  74 -       mtk_w32(eth, val, TRGMII_TCK_CTRL);
  75 +       dev_err(eth->dev, "Missing PLL configuration, ethernet may not work\n");
  76  }
  77
  78  static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
  79 @@ -471,17 +452,8 @@ static void mtk_mac_config(struct phylin
  80                                                               state->interface))
  81                                         goto err_phy;
  82                         } else {
  83 -                               /* FIXME: this is incorrect. Not only does it
  84 -                                * use state->speed (which is not guaranteed
  85 -                                * to be correct) but it also makes use of it
  86 -                                * in a code path that will only be reachable
  87 -                                * when the PHY interface mode changes, not
  88 -                                * when the speed changes. Consequently, RGMII
  89 -                                * is probably broken.
  90 -                                */
  91                                 mtk_gmac0_rgmii_adjust(mac->hw,
  92 -                                                      state->interface,
  93 -                                                      state->speed);
  94 +                                                      state->interface);
  95
  96                                 /* mt7623_pad_clk_setup */
  97                                 for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
  98 @@ -4340,13 +4312,19 @@ static int mtk_add_mac(struct mtk_eth *e
  99         mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
 100                 MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
 101
 102 -       __set_bit(PHY_INTERFACE_MODE_MII,
 103 -                 mac->phylink_config.supported_interfaces);
 104 -       __set_bit(PHY_INTERFACE_MODE_GMII,
 105 -                 mac->phylink_config.supported_interfaces);
 106 +       /* MT7623 gmac0 is now missing its speed-specific PLL configuration
 107 +        * in its .mac_config method (since state->speed is not valid there.
 108 +        * Disable support for MII, GMII and RGMII.
 109 +        */
 110 +       if (!mac->hw->soc->disable_pll_modes || mac->id != 0) {
 111 +               __set_bit(PHY_INTERFACE_MODE_MII,
 112 +                         mac->phylink_config.supported_interfaces);
 113 +               __set_bit(PHY_INTERFACE_MODE_GMII,
 114 +                         mac->phylink_config.supported_interfaces);
 115
 116 -       if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
 117 -               phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
 118 +               if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_RGMII))
 119 +                       phy_interface_set_rgmii(mac->phylink_config.supported_interfaces);
 120 +       }
 121
 122         if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
 123                 __set_bit(PHY_INTERFACE_MODE_TRGMII,
 124 @@ -4804,6 +4782,7 @@ static const struct mtk_soc_data mt7623_
 125         .offload_version = 1,
 126         .hash_offset = 2,
 127         .foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
 128 +       .disable_pll_modes = true,
 129         .txrx = {
 130                 .txd_size = sizeof(struct mtk_tx_dma),
 131                 .rxd_size = sizeof(struct mtk_rx_dma),
 132 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 133 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 134 @@ -1030,6 +1030,7 @@ struct mtk_soc_data {
 135         u16             foe_entry_size;
 136         netdev_features_t hw_features;
 137         bool            has_accounting;
 138 +       bool            disable_pll_modes;
 139         struct {
 140                 u32     txd_size;
 141                 u32     rxd_size;