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1 From 229d32330c7d941b8e04501ad75bc527f6cf1b1c Mon Sep 17 00:00:00 2001
2 From: Li Yang <leoyang.li@nxp.com>
3 Date: Thu, 2 May 2019 16:06:42 -0500
4 Subject: [PATCH] arm64: dts: ls1046a: accumulated change to ls1046a boards
5
6 commit 118e2f48ee8da3f5547c24888bd6fdb78f03b7ce
7 Author: Peng Ma <peng.ma@nxp.com>
8 Date: Wed Jul 25 08:53:07 2018 +0000
9
10 dts: fsl-ls1021a, fsl-ls1043a, fsl-ls1046a: add multi block node
11 support
12
13 add block-offset to support different virtual block offset for qdma
14 base on soc;
15 the interrupt named "qdma-queueN(N:0,1,2,3)" correspond to a virtual
16 block,N based on block number of qdma;
17
18 Signed-off-by: Peng Ma <peng.ma@nxp.com>
19
20 commit 46123df3a174f0d76c8b954a0386e64841453836
21 Author: Florinel Iordache <florinel.iordache@nxp.com>
22 Date: Thu Aug 9 12:29:18 2018 +0300
23
24 arm64: dts: updates for Unified Backplane driver
25
26 Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
27
28 commit c08136017e8b18eb58b153129487c5dc760afd20
29 Author: Florinel Iordache <florinel.iordache@nxp.com>
30 Date: Thu Aug 9 12:23:42 2018 +0300
31
32 arm64: dts: ls1046: add support for 10GBase-KR
33
34 Signed-off-by: Florinel Iordache <florinel.iordache@nxp.com>
35
36 commit 8473f478783f6f601e1c6d7e6afba49a13f3a6a3
37 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
38 Date: Mon Apr 2 16:24:33 2018 +0800
39
40 arm64: dts: ls1046a: add dts entry for A-010650
41
42 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
43
44 commit 3159fe9263fb145601ccb07fcb9336a68fba4e08
45 Author: Bao Xiaowei <xiaowei.bao@nxp.com>
46 Date: Fri Oct 13 11:04:39 2017 +0800
47
48 arm64: dts: ls1046a: add the property of IB and OB
49
50 Add the property of inbound and outbound windows number for ep
51 driver.
52
53 Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com>
54
55 Acked-by: Minghuan Lian <minghuan.Lian@nxp.com>
56 Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
57
58 commit c8fed58f3c9a0219fda0467791f61abd86eb97f3
59 Author: Abhimanyu Saini <abhimanyu.saini@nxp.com>
60 Date: Wed Jan 24 22:56:48 2018 +0530
61
62 arm64: dts: freescale: ls1046a: Modify DT nodes for qspi
63
64 Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
65
66 commit 96558859ea3a4af44c0b25441f7574ae6222509a
67 Author: Ran Wang <ran.wang_1@nxp.com>
68 Date: Fri Jan 5 15:17:23 2018 +0800
69
70 arm64: dts: ls1046a: Enable usb3-lpm-capable for usb3 node
71
72 Enable USB3 HW LPM feature for ls1046a and active patch for
73 snps erratum A-010131. It will disable U1/U2 temperary when
74 initiate U3 request.
75
76 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
77
78 commit 9b17a5fcf8da5656ff99ebef3d63ba040e9f676d
79 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
80 Date: Tue Jun 13 13:14:26 2017 +0800
81
82 arm64: dts: correct the register range of dcfg
83
84 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
85
86 commit 67c82e3c7b376139d7cee624589bedbc311f8868
87 Author: jiaheng.fan <jiaheng.fan@nxp.com>
88 Date: Thu May 11 17:36:33 2017 +0800
89
90 arm64: dts: ls1021/ls1043/ls1046: add qdma nodes
91
92 Signed-off-by: jiaheng.fan <jiaheng.fan@nxp.com>
93
94 commit 4a6cef0c83748ee4f6641489fc324bd64095485d
95 Author: Chenhui Zhao <chenhui.zhao@nxp.com>
96 Date: Fri May 5 17:53:27 2017 +0800
97
98 arm64: dts: ls1046a: add ftm0 node
99
100 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
101 ---
102 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts | 148 ++++++++++++++++++++++
103 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 1 +
104 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 28 +++-
105 3 files changed, 174 insertions(+), 3 deletions(-)
106
107 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
108 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts
109 @@ -25,6 +25,20 @@
110 serial1 = &duart1;
111 serial2 = &duart2;
112 serial3 = &duart3;
113 +
114 + emi1_slot1 = &ls1046mdio_s1;
115 + emi1_slot2 = &ls1046mdio_s2;
116 + emi1_slot4 = &ls1046mdio_s4;
117 +
118 + sgmii_s1_p1 = &sgmii_phy_s1_p1;
119 + sgmii_s1_p2 = &sgmii_phy_s1_p2;
120 + sgmii_s1_p3 = &sgmii_phy_s1_p3;
121 + sgmii_s1_p4 = &sgmii_phy_s1_p4;
122 + sgmii_s4_p1 = &sgmii_phy_s4_p1;
123 + qsgmii_s2_p1 = &qsgmii_phy_s2_p1;
124 + qsgmii_s2_p2 = &qsgmii_phy_s2_p2;
125 + qsgmii_s2_p3 = &qsgmii_phy_s2_p3;
126 + qsgmii_s2_p4 = &qsgmii_phy_s2_p4;
127 };
128
129 chosen {
130 @@ -177,3 +191,137 @@
131 };
132
133 #include "fsl-ls1046-post.dtsi"
134 +
135 +&fman0 {
136 + ethernet@e0000 {
137 + phy-handle = <&qsgmii_phy_s2_p1>;
138 + phy-connection-type = "sgmii";
139 + };
140 +
141 + ethernet@e2000 {
142 + phy-handle = <&sgmii_phy_s4_p1>;
143 + phy-connection-type = "sgmii";
144 + };
145 +
146 + ethernet@e4000 {
147 + phy-handle = <&rgmii_phy1>;
148 + phy-connection-type = "rgmii";
149 + };
150 +
151 + ethernet@e6000 {
152 + phy-handle = <&rgmii_phy2>;
153 + phy-connection-type = "rgmii";
154 + };
155 +
156 + ethernet@e8000 {
157 + phy-handle = <&sgmii_phy_s1_p3>;
158 + phy-connection-type = "sgmii";
159 + };
160 +
161 + ethernet@ea000 {
162 + phy-handle = <&sgmii_phy_s1_p4>;
163 + phy-connection-type = "sgmii";
164 + };
165 +
166 + ethernet@f0000 { /* DTSEC9/10GEC1 */
167 + phy-handle = <&sgmii_phy_s1_p1>;
168 + phy-connection-type = "xgmii";
169 + };
170 +
171 + ethernet@f2000 { /* DTSEC10/10GEC2 */
172 + phy-handle = <&sgmii_phy_s1_p2>;
173 + phy-connection-type = "xgmii";
174 + };
175 +};
176 +
177 +&fpga {
178 + #address-cells = <1>;
179 + #size-cells = <1>;
180 + mdio-mux-emi1 {
181 + compatible = "mdio-mux-mmioreg", "mdio-mux";
182 + mdio-parent-bus = <&mdio0>;
183 + #address-cells = <1>;
184 + #size-cells = <0>;
185 + reg = <0x54 1>; /* BRDCFG4 */
186 + mux-mask = <0xe0>; /* EMI1 */
187 +
188 + /* On-board RGMII1 PHY */
189 + ls1046mdio0: mdio@0 {
190 + reg = <0>;
191 + #address-cells = <1>;
192 + #size-cells = <0>;
193 +
194 + rgmii_phy1: ethernet-phy@1 { /* MAC3 */
195 + reg = <0x1>;
196 + };
197 + };
198 +
199 + /* On-board RGMII2 PHY */
200 + ls1046mdio1: mdio@1 {
201 + reg = <0x20>;
202 + #address-cells = <1>;
203 + #size-cells = <0>;
204 +
205 + rgmii_phy2: ethernet-phy@2 { /* MAC4 */
206 + reg = <0x2>;
207 + };
208 + };
209 +
210 + /* Slot 1 */
211 + ls1046mdio_s1: mdio@2 {
212 + reg = <0x40>;
213 + #address-cells = <1>;
214 + #size-cells = <0>;
215 + status = "disabled";
216 +
217 + sgmii_phy_s1_p1: ethernet-phy@1c {
218 + reg = <0x1c>;
219 + };
220 +
221 + sgmii_phy_s1_p2: ethernet-phy@1d {
222 + reg = <0x1d>;
223 + };
224 +
225 + sgmii_phy_s1_p3: ethernet-phy@1e {
226 + reg = <0x1e>;
227 + };
228 +
229 + sgmii_phy_s1_p4: ethernet-phy@1f {
230 + reg = <0x1f>;
231 + };
232 + };
233 +
234 + /* Slot 2 */
235 + ls1046mdio_s2: mdio@3 {
236 + reg = <0x60>;
237 + #address-cells = <1>;
238 + #size-cells = <0>;
239 + status = "disabled";
240 +
241 + qsgmii_phy_s2_p1: ethernet-phy@8 {
242 + reg = <0x8>;
243 + };
244 + qsgmii_phy_s2_p2: ethernet-phy@9 {
245 + reg = <0x9>;
246 + };
247 + qsgmii_phy_s2_p3: ethernet-phy@a {
248 + reg = <0xa>;
249 + };
250 + qsgmii_phy_s2_p4: ethernet-phy@b {
251 + reg = <0xb>;
252 + };
253 + };
254 +
255 + /* Slot 4 */
256 + ls1046mdio_s4: mdio@5 {
257 + reg = <0x80>;
258 + #address-cells = <1>;
259 + #size-cells = <0>;
260 + status = "disabled";
261 +
262 + sgmii_phy_s4_p1: ethernet-phy@1c {
263 + reg = <0x1c>;
264 + };
265 + };
266 + };
267 +};
268 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
269 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
270 @@ -100,6 +100,7 @@
271
272 &qspi {
273 status = "okay";
274 + fsl,qspi-has-second-chip;
275
276 qflash0: flash@0 {
277 compatible = "spansion,m25p80";
278 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
279 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
280 @@ -304,7 +304,7 @@
281
282 dcfg: dcfg@1ee0000 {
283 compatible = "fsl,ls1046a-dcfg", "syscon";
284 - reg = <0x0 0x1ee0000 0x0 0x10000>;
285 + reg = <0x0 0x1ee0000 0x0 0x1000>;
286 big-endian;
287 };
288
289 @@ -376,7 +376,7 @@
290 };
291
292 i2c0: i2c@2180000 {
293 - compatible = "fsl,vf610-i2c";
294 + compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
295 #address-cells = <1>;
296 #size-cells = <0>;
297 reg = <0x0 0x2180000 0x0 0x10000>;
298 @@ -385,6 +385,7 @@
299 dmas = <&edma0 1 39>,
300 <&edma0 1 38>;
301 dma-names = "tx", "rx";
302 + scl-gpios = <&gpio3 12 0>;
303 status = "disabled";
304 };
305
306 @@ -409,12 +410,13 @@
307 };
308
309 i2c3: i2c@21b0000 {
310 - compatible = "fsl,vf610-i2c";
311 + compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c";
312 #address-cells = <1>;
313 #size-cells = <0>;
314 reg = <0x0 0x21b0000 0x0 0x10000>;
315 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&clockgen 4 1>;
317 + scl-gpios = <&gpio3 12 0>;
318 status = "disabled";
319 };
320
321 @@ -544,6 +546,15 @@
322 status = "disabled";
323 };
324
325 + ftm0: ftm0@29d0000 {
326 + compatible = "fsl,ftm-alarm";
327 + reg = <0x0 0x29d0000 0x0 0x10000>,
328 + <0x0 0x1ee2140 0x0 0x4>;
329 + reg-names = "ftm", "FlexTimer1";
330 + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
331 + big-endian;
332 + };
333 +
334 wdog0: watchdog@2ad0000 {
335 compatible = "fsl,imx21-wdt";
336 reg = <0x0 0x2ad0000 0x0 0x10000>;
337 @@ -576,6 +587,8 @@
338 snps,quirk-frame-length-adjustment = <0x20>;
339 snps,dis_rxdet_inp3_quirk;
340 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
341 + usb3-lpm-capable;
342 + snps,dis-u1u2-when-u3-quirk;
343 };
344
345 usb1: usb@3000000 {
346 @@ -586,6 +599,8 @@
347 snps,quirk-frame-length-adjustment = <0x20>;
348 snps,dis_rxdet_inp3_quirk;
349 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
350 + usb3-lpm-capable;
351 + snps,dis-u1u2-when-u3-quirk;
352 };
353
354 usb2: usb@3100000 {
355 @@ -596,6 +611,8 @@
356 snps,quirk-frame-length-adjustment = <0x20>;
357 snps,dis_rxdet_inp3_quirk;
358 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>;
359 + usb3-lpm-capable;
360 + snps,dis-u1u2-when-u3-quirk;
361 };
362
363 sata: sata@3200000 {
364 @@ -637,6 +654,11 @@
365 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
366 };
367
368 + serdes1: serdes@1ea0000 {
369 + reg = <0x0 0x1ea0000 0 0x00002000>;
370 + compatible = "fsl,serdes-10g";
371 + };
372 +
373 pcie@3400000 {
374 compatible = "fsl,ls1046a-pcie";
375 reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */
Staging tree of Piotr Dymacz