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1 From a4f577bc6a231542ed348fec6d2c00d813a411cd Mon Sep 17 00:00:00 2001
2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
3 Date: Mon, 25 Sep 2023 16:57:07 +0100
4 Subject: [PATCH 0598/1085] drm/vc4: Move the buffer offset out of the
5 vc4_plane_state
6
7 The offset fields in vc4_plane_state are described as being
8 the offset for each buffer in the bo, however it is used to
9 store the complete DMA address that is then written into the
10 register.
11
12 The DMA address including the fb ofset can be retrieved
13 using drm_fb_dma_get_gem_addr, and the offset adjustment due to
14 clipping is local to vc4_plane_mode_set.
15 Drop the offset field from the state, and compute the complete
16 DMA address in vc4_plane_mode_set.
17
18 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
19 ---
20 drivers/gpu/drm/vc4/vc4_drv.h | 5 ----
21 drivers/gpu/drm/vc4/vc4_plane.c | 51 +++++++++++++--------------------
22 2 files changed, 20 insertions(+), 36 deletions(-)
23
24 --- a/drivers/gpu/drm/vc4/vc4_drv.h
25 +++ b/drivers/gpu/drm/vc4/vc4_drv.h
26 @@ -431,11 +431,6 @@ struct vc4_plane_state {
27 bool is_unity;
28 bool is_yuv;
29
30 - /* Offset to start scanning out from the start of the plane's
31 - * BO.
32 - */
33 - u32 offsets[3];
34 -
35 /* Our allocation in LBM for temporary storage during scaling. */
36 struct drm_mm_node lbm;
37
38 --- a/drivers/gpu/drm/vc4/vc4_plane.c
39 +++ b/drivers/gpu/drm/vc4/vc4_plane.c
40 @@ -450,12 +450,11 @@ static int vc4_plane_setup_clipping_and_
41 {
42 struct vc4_plane_state *vc4_state = to_vc4_plane_state(state);
43 struct drm_framebuffer *fb = state->fb;
44 - struct drm_gem_dma_object *bo;
45 int num_planes = fb->format->num_planes;
46 struct drm_crtc_state *crtc_state;
47 u32 h_subsample = fb->format->hsub;
48 u32 v_subsample = fb->format->vsub;
49 - int i, ret;
50 + int ret;
51
52 crtc_state = drm_atomic_get_existing_crtc_state(state->state,
53 state->crtc);
54 @@ -469,11 +468,6 @@ static int vc4_plane_setup_clipping_and_
55 if (ret)
56 return ret;
57
58 - for (i = 0; i < num_planes; i++) {
59 - bo = drm_fb_dma_get_gem_obj(fb, i);
60 - vc4_state->offsets[i] = bo->dma_addr + fb->offsets[i];
61 - }
62 -
63 vc4_state->src_x = state->src.x1;
64 vc4_state->src_y = state->src.y1;
65 vc4_state->src_w[0] = state->src.x2 - vc4_state->src_x;
66 @@ -896,6 +890,7 @@ static int vc4_plane_mode_set(struct drm
67 u32 width, height;
68 u32 hvs_format = format->hvs;
69 unsigned int rotation;
70 + u32 offsets[3] = { 0 };
71 int ret, i;
72
73 if (vc4_state->dlist_initialized)
74 @@ -943,13 +938,8 @@ static int vc4_plane_mode_set(struct drm
75 * out.
76 */
77 for (i = 0; i < num_planes; i++) {
78 - vc4_state->offsets[i] += src_y /
79 - (i ? v_subsample : 1) *
80 - fb->pitches[i];
81 -
82 - vc4_state->offsets[i] += src_x /
83 - (i ? h_subsample : 1) *
84 - fb->format->cpp[i];
85 + offsets[i] += src_y / (i ? v_subsample : 1) * fb->pitches[i];
86 + offsets[i] += src_x / (i ? h_subsample : 1) * fb->format->cpp[i];
87 }
88
89 break;
90 @@ -1004,19 +994,18 @@ static int vc4_plane_mode_set(struct drm
91 VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
92 VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
93 VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
94 - vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
95 - vc4_state->offsets[0] += subtile_y << 8;
96 - vc4_state->offsets[0] += utile_y << 4;
97 + offsets[0] += tiles_t * (tiles_w << tile_size_shift);
98 + offsets[0] += subtile_y << 8;
99 + offsets[0] += utile_y << 4;
100
101 /* Rows of tiles alternate left-to-right and right-to-left. */
102 if (tiles_t & 1) {
103 pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
104 - vc4_state->offsets[0] += (tiles_w - tiles_l) <<
105 - tile_size_shift;
106 - vc4_state->offsets[0] -= (1 + !tile_y) << 10;
107 + offsets[0] += (tiles_w - tiles_l) << tile_size_shift;
108 + offsets[0] -= (1 + !tile_y) << 10;
109 } else {
110 - vc4_state->offsets[0] += tiles_l << tile_size_shift;
111 - vc4_state->offsets[0] += tile_y << 10;
112 + offsets[0] += tiles_l << tile_size_shift;
113 + offsets[0] += tile_y << 10;
114 }
115
116 break;
117 @@ -1105,11 +1094,9 @@ static int vc4_plane_mode_set(struct drm
118
119 tile = src_x / pix_per_tile;
120
121 - vc4_state->offsets[i] += param * tile_w * tile;
122 - vc4_state->offsets[i] += src_y /
123 - (i ? v_subsample : 1) *
124 - tile_w;
125 - vc4_state->offsets[i] += x_off & ~(i ? 1 : 0);
126 + offsets[i] += param * tile_w * tile;
127 + offsets[i] += src_y / (i ? v_subsample : 1) * tile_w;
128 + offsets[i] += x_off & ~(i ? 1 : 0);
129 }
130
131 pitch0 = VC4_SET_FIELD(param, SCALER_TILE_HEIGHT);
132 @@ -1253,8 +1240,12 @@ static int vc4_plane_mode_set(struct drm
133 * The pointers may be any byte address.
134 */
135 vc4_state->ptr0_offset[0] = vc4_state->dlist_count;
136 - for (i = 0; i < num_planes; i++)
137 - vc4_dlist_write(vc4_state, vc4_state->offsets[i]);
138 +
139 + for (i = 0; i < num_planes; i++) {
140 + dma_addr_t paddr = drm_fb_dma_get_gem_addr(fb, state, i);
141 +
142 + vc4_dlist_write(vc4_state, paddr + offsets[i]);
143 + }
144
145 /* Pointer Context Word 0/1/2: Written by the HVS */
146 for (i = 0; i < num_planes; i++)
147 @@ -1517,8 +1508,6 @@ static void vc4_plane_atomic_async_updat
148 sizeof(vc4_state->y_scaling));
149 vc4_state->is_unity = new_vc4_state->is_unity;
150 vc4_state->is_yuv = new_vc4_state->is_yuv;
151 - memcpy(vc4_state->offsets, new_vc4_state->offsets,
152 - sizeof(vc4_state->offsets));
153 vc4_state->needs_bg_fill = new_vc4_state->needs_bg_fill;
154
155 /* Update the current vc4_state pos0, pos2 and ptr0 dlist entries. */
Staging tree of David Bauer