git.openwrt.org Git - openwrt/staging/rmilecki.git/blob

   1 From ae5dad214ec109cdeffd3fac5ce4be6ab59a0283 Mon Sep 17 00:00:00 2001
   2 From: Kuldeep Singh <kuldeep.singh@nxp.com>
   3 Date: Fri, 3 Jan 2020 14:49:07 +0530
   4 Subject: [PATCH] LF-18-2 arm64: dts: ls1046ardb: Update qspi node dts
   5  properties
   6
   7 Use compatibles as "jedec,spi-nor" to probe flash without displaying
   8 warning: found s25fs512s, expected m25p80.
   9 Remove "fsl,qspi-has-second-chip" as new driver doesn't use it anymore.
  10 Update rx and tx width to 1.
  11
  12 Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com>
  13 ---
  14  arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts | 17 ++++++++---------
  15  1 file changed, 8 insertions(+), 9 deletions(-)
  16
  17 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
  18 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts
  19 @@ -105,25 +105,24 @@
  20
  21  &qspi {
  22         status = "okay";
  23 -       fsl,qspi-has-second-chip;
  24
  25 -       qflash0: flash@0 {
  26 -               compatible = "spansion,m25p80";
  27 +       s25fs512s0: flash@0 {
  28 +               compatible = "jedec,spi-nor";
  29                 #address-cells = <1>;
  30                 #size-cells = <1>;
  31                 spi-max-frequency = <50000000>;
  32 -               spi-rx-bus-width = <4>;
  33 -               spi-tx-bus-width = <4>;
  34 +               spi-rx-bus-width = <1>;
  35 +               spi-tx-bus-width = <1>;
  36                 reg = <0>;
  37         };
  38
  39 -       qflash1: flash@1 {
  40 -               compatible = "spansion,m25p80";
  41 +       s25fs512s: flash@1 {
  42 +               compatible = "jedec,spi-nor";
  43                 #address-cells = <1>;
  44                 #size-cells = <1>;
  45                 spi-max-frequency = <50000000>;
  46 -               spi-rx-bus-width = <4>;
  47 -               spi-tx-bus-width = <4>;
  48 +               spi-rx-bus-width = <1>;
  49 +               spi-tx-bus-width = <1>;
  50                 reg = <1>;
  51         };
  52  };