git.openwrt.org Git - openwrt/staging/neocturne.git/blob

   1 From 5a91c439cbeb1f64b8b9830de91efad5113d3c89 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Fri, 14 May 2021 15:52:11 +0200
   4 Subject: [PATCH] fix(plat/marvell/a3720/uart): fix UART parent clock rate
   5  determination
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 The UART code for the A3K platform assumes that UART parent clock rate
  11 is always 25 MHz. This is incorrect, because the xtal clock can also run
  12 at 40 MHz (this is board specific).
  13
  14 The frequency of the xtal clock is determined by a value on a strapping
  15 pin during SOC reset. The code to determine this frequency is already in
  16 A3K's comphy driver.
  17
  18 Move the get_ref_clk() function from the comphy driver to a separate
  19 file and use it for UART parent clock rate determination.
  20
  21 Signed-off-by: Pali Rohár <pali@kernel.org>
  22 Change-Id: I8bb18a2d020ef18fe65aa06ffa4ab205c71be92e
  23 ---
  24  drivers/marvell/comphy/phy-comphy-3700.c      | 24 +------------
  25  .../marvell/armada/a3k/common/plat_marvell.h  |  2 ++
  26  .../marvell/armada/a3k/common/a3700_common.mk |  1 +
  27  .../armada/a3k/common/aarch64/a3700_clock.S   | 35 +++++++++++++++++++
  28  .../armada/a3k/common/include/platform_def.h  |  1 -
  29  .../armada/common/aarch64/marvell_helpers.S   | 10 +++++-
  30  plat/marvell/armada/common/marvell_console.c  |  1 +
  31  7 files changed, 49 insertions(+), 25 deletions(-)
  32  create mode 100644 plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
  33
  34 --- a/drivers/marvell/comphy/phy-comphy-3700.c
  35 +++ b/drivers/marvell/comphy/phy-comphy-3700.c
  36 @@ -14,6 +14,7 @@
  37
  38  #include <mvebu.h>
  39  #include <mvebu_def.h>
  40 +#include <plat_marvell.h>
  41
  42  #include "phy-comphy-3700.h"
  43  #include "phy-comphy-common.h"
  44 @@ -29,15 +30,6 @@
  45  #define USB3_GBE1_PHY          (MVEBU_REGS_BASE + 0x5C000)
  46  #define COMPHY_SD_ADDR         (MVEBU_REGS_BASE + 0x1F000)
  47
  48 -/*
  49 - * Below address in used only for reading, therefore no problem with concurrent
  50 - * Linux access.
  51 - */
  52 -#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
  53 - #define MVEBU_XTAL_MODE_MASK          BIT(9)
  54 - #define MVEBU_XTAL_MODE_OFFS          9
  55 - #define MVEBU_XTAL_CLOCK_25MHZ                0x0
  56 -
  57  struct sgmii_phy_init_data_fix {
  58         uint16_t addr;
  59         uint16_t value;
  60 @@ -125,20 +117,6 @@ static uint16_t sgmii_phy_init[512] = {
  61         0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000  /*1F8 */
  62  };
  63
  64 -/* returns reference clock in MHz (25 or 40) */
  65 -static uint32_t get_ref_clk(void)
  66 -{
  67 -       uint32_t val;
  68 -
  69 -       val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
  70 -               MVEBU_XTAL_MODE_OFFS;
  71 -
  72 -       if (val == MVEBU_XTAL_CLOCK_25MHZ)
  73 -               return 25;
  74 -       else
  75 -               return 40;
  76 -}
  77 -
  78  /* PHY selector configures with corresponding modes */
  79  static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
  80                                                 uint32_t comphy_mode)
  81 --- a/include/plat/marvell/armada/a3k/common/plat_marvell.h
  82 +++ b/include/plat/marvell/armada/a3k/common/plat_marvell.h
  83 @@ -100,4 +100,6 @@ void plat_marvell_interconnect_enter_coh
  84
  85  const mmap_region_t *plat_marvell_get_mmap(void);
  86
  87 +uint32_t get_ref_clk(void);
  88 +
  89  #endif /* PLAT_MARVELL_H */
  90 --- a/plat/marvell/armada/a3k/common/a3700_common.mk
  91 +++ b/plat/marvell/armada/a3k/common/a3700_common.mk
  92 @@ -38,6 +38,7 @@ PLAT_INCLUDES         :=      -I$(PLAT_FAMILY_BASE)/
  93                                 -I$/drivers/arm/gic/common/
  94
  95  PLAT_BL_COMMON_SOURCES :=      $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
  96 +                               $(PLAT_COMMON_BASE)/aarch64/a3700_clock.S \
  97                                 $(MARVELL_DRV_BASE)/uart/a3700_console.S
  98
  99  BL1_SOURCES            +=      $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
 100 --- /dev/null
 101 +++ b/plat/marvell/armada/a3k/common/aarch64/a3700_clock.S
 102 @@ -0,0 +1,35 @@
 103 +/*
 104 + * Copyright (C) 2018 Marvell International Ltd.
 105 + *
 106 + * SPDX-License-Identifier:    BSD-3-Clause
 107 + * https://spdx.org/licenses
 108 + */
 109 +
 110 +#include <asm_macros.S>
 111 +#include <platform_def.h>
 112 +
 113 +/*
 114 + * Below address in used only for reading, therefore no problem with concurrent
 115 + * Linux access.
 116 + */
 117 +#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
 118 + #define MVEBU_XTAL_MODE_MASK          BIT(9)
 119 +
 120 +       /* -----------------------------------------------------
 121 +        * uint32_t get_ref_clk (void);
 122 +        *
 123 +        * returns reference clock in MHz (25 or 40)
 124 +        * -----------------------------------------------------
 125 +        */
 126 +.globl get_ref_clk
 127 +func get_ref_clk
 128 +       mov_imm x0, MVEBU_TEST_PIN_LATCH_N
 129 +       ldr     w0, [x0]
 130 +       tst     w0, #MVEBU_XTAL_MODE_MASK
 131 +       bne     40
 132 +       mov     w0, #25
 133 +       ret
 134 +40:
 135 +       mov     w0, #40
 136 +       ret
 137 +endfunc get_ref_clk
 138 --- a/plat/marvell/armada/a3k/common/include/platform_def.h
 139 +++ b/plat/marvell/armada/a3k/common/include/platform_def.h
 140 @@ -164,7 +164,6 @@
 141   * PL011 related constants
 142   */
 143  #define PLAT_MARVELL_UART_BASE                 (MVEBU_REGS_BASE + 0x12000)
 144 -#define PLAT_MARVELL_UART_CLK_IN_HZ            25000000
 145
 146  #define PLAT_MARVELL_BL31_RUN_UART_BASE                PLAT_MARVELL_BOOT_UART_BASE
 147  #define PLAT_MARVELL_BL31_RUN_UART_CLK_IN_HZ   PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
 148 --- a/plat/marvell/armada/common/aarch64/marvell_helpers.S
 149 +++ b/plat/marvell/armada/common/aarch64/marvell_helpers.S
 150 @@ -63,8 +63,16 @@ endfunc plat_marvell_calc_core_pos
 151          * ---------------------------------------------
 152          */
 153  func plat_crash_console_init
 154 -       mov_imm x0, PLAT_MARVELL_UART_BASE
 155 +#ifdef PLAT_a3700
 156 +       mov     x1, x30
 157 +       bl      get_ref_clk
 158 +       mov     x30, x1
 159 +       mov_imm x1, 1000000
 160 +       mul     x1, x0, x1
 161 +#else
 162         mov_imm x1, PLAT_MARVELL_UART_CLK_IN_HZ
 163 +#endif
 164 +       mov_imm x0, PLAT_MARVELL_UART_BASE
 165         mov_imm x2, MARVELL_CONSOLE_BAUDRATE
 166  #ifdef PLAT_a3700
 167         b       console_a3700_core_init
 168 --- a/plat/marvell/armada/common/marvell_console.c
 169 +++ b/plat/marvell/armada/common/marvell_console.c
 170 @@ -14,6 +14,7 @@
 171
 172  #ifdef PLAT_a3700
 173  #include <drivers/marvell/uart/a3700_console.h>
 174 +#define PLAT_MARVELL_UART_CLK_IN_HZ (get_ref_clk() * 1000000)
 175  #define console_marvell_register console_a3700_register
 176  #else
 177  #include <drivers/ti/uart/uart_16550.h>