git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 0c024632c1e7ff69914329bfd87bec749b9c0aed Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Wed, 2 Aug 2023 04:31:09 +0100
   4 Subject: [PATCH 108/250] net: ethernet: mtk_eth_soc: support per-flow
   5  accounting on MT7988
   6
   7 NETSYS_V3 uses 64 bits for each counters while older SoCs are using
   8 48/40 bits for each counter.
   9 Support reading per-flow byte and package counters on NETSYS_V3.
  10
  11 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  12 Reviewed-by: Simon Horman <horms@kernel.org>
  13 Link: https://lore.kernel.org/r/37a0928fa8c1253b197884c68ce1f54239421ac5.1690946442.git.daniel@makrotopia.org
  14 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  15 ---
  16  drivers/net/ethernet/mediatek/mtk_eth_soc.c  |  1 +
  17  drivers/net/ethernet/mediatek/mtk_ppe.c      | 21 +++++++++++++-------
  18  drivers/net/ethernet/mediatek/mtk_ppe_regs.h |  2 ++
  19  3 files changed, 17 insertions(+), 7 deletions(-)
  20
  21 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  22 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
  23 @@ -4979,6 +4979,7 @@ static const struct mtk_soc_data mt7988_
  24         .version = 3,
  25         .offload_version = 2,
  26         .hash_offset = 4,
  27 +       .has_accounting = true,
  28         .foe_entry_size = MTK_FOE_ENTRY_V3_SIZE,
  29         .txrx = {
  30                 .txd_size = sizeof(struct mtk_tx_dma_v2),
  31 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
  32 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
  33 @@ -91,7 +91,6 @@ static int mtk_ppe_mib_wait_busy(struct
  34
  35  static int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *packets)
  36  {
  37 -       u32 byte_cnt_low, byte_cnt_high, pkt_cnt_low, pkt_cnt_high;
  38         u32 val, cnt_r0, cnt_r1, cnt_r2;
  39         int ret;
  40
  41 @@ -106,12 +105,20 @@ static int mtk_mib_entry_read(struct mtk
  42         cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1);
  43         cnt_r2 = readl(ppe->base + MTK_PPE_MIB_SER_R2);
  44
  45 -       byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0);
  46 -       byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1);
  47 -       pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1);
  48 -       pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2);
  49 -       *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low;
  50 -       *packets = (pkt_cnt_high << 16) | pkt_cnt_low;
  51 +       if (mtk_is_netsys_v3_or_greater(ppe->eth)) {
  52 +               /* 64 bit for each counter */
  53 +               u32 cnt_r3 = readl(ppe->base + MTK_PPE_MIB_SER_R3);
  54 +               *bytes = ((u64)cnt_r1 << 32) | cnt_r0;
  55 +               *packets = ((u64)cnt_r3 << 32) | cnt_r2;
  56 +       } else {
  57 +               /* 48 bit byte counter, 40 bit packet counter */
  58 +               u32 byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0);
  59 +               u32 byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1);
  60 +               u32 pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1);
  61 +               u32 pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2);
  62 +               *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low;
  63 +               *packets = (pkt_cnt_high << 16) | pkt_cnt_low;
  64 +       }
  65
  66         return 0;
  67  }
  68 --- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
  69 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
  70 @@ -163,6 +163,8 @@ enum {
  71  #define MTK_PPE_MIB_SER_R2                     0x348
  72  #define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH                GENMASK(23, 0)
  73
  74 +#define MTK_PPE_MIB_SER_R3                     0x34c
  75 +
  76  #define MTK_PPE_MIB_CACHE_CTL                  0x350
  77  #define MTK_PPE_MIB_CACHE_CTL_EN               BIT(0)
  78  #define MTK_PPE_MIB_CACHE_CTL_FLUSH            BIT(2)