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1 From e5ecb4f619197b93fa682d722452dc8412864cdb Mon Sep 17 00:00:00 2001
2 Message-Id: <e5ecb4f619197b93fa682d722452dc8412864cdb.1662886033.git.lorenzo@kernel.org>
3 From: Lorenzo Bianconi <lorenzo@kernel.org>
4 Date: Fri, 26 Aug 2022 01:12:57 +0200
5 Subject: [PATCH net-next 1/5] net: ethernet: mtk_eth_wed: add
6 mtk_wed_configure_irq and mtk_wed_dma_{enable/disable}
7
8 Introduce mtk_wed_configure_irq, mtk_wed_dma_enable and mtk_wed_dma_disable
9 utility routines.
10 This is a preliminary patch to introduce mt7986 wed support.
11
12 Co-developed-by: Bo Jiao <Bo.Jiao@mediatek.com>
13 Signed-off-by: Bo Jiao <Bo.Jiao@mediatek.com>
14 Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
15 Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
16 Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
17 ---
18 drivers/net/ethernet/mediatek/mtk_wed.c | 87 +++++++++++++-------
19 drivers/net/ethernet/mediatek/mtk_wed_regs.h | 6 +-
20 2 files changed, 64 insertions(+), 29 deletions(-)
21
22 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
23 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
24 @@ -237,9 +237,30 @@ mtk_wed_set_ext_int(struct mtk_wed_devic
25 }
26
27 static void
28 -mtk_wed_stop(struct mtk_wed_device *dev)
29 +mtk_wed_dma_disable(struct mtk_wed_device *dev)
30 {
31 + wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
32 + MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
33 + MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
34 +
35 + wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
36 +
37 + wed_clr(dev, MTK_WED_GLO_CFG,
38 + MTK_WED_GLO_CFG_TX_DMA_EN |
39 + MTK_WED_GLO_CFG_RX_DMA_EN);
40 +
41 regmap_write(dev->hw->mirror, dev->hw->index * 4, 0);
42 + wdma_m32(dev, MTK_WDMA_GLO_CFG,
43 + MTK_WDMA_GLO_CFG_TX_DMA_EN |
44 + MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
45 + MTK_WDMA_GLO_CFG_RX_INFO2_PRERES |
46 + MTK_WDMA_GLO_CFG_RX_INFO3_PRERES, 0);
47 +}
48 +
49 +static void
50 +mtk_wed_stop(struct mtk_wed_device *dev)
51 +{
52 + mtk_wed_dma_disable(dev);
53 mtk_wed_set_ext_int(dev, false);
54
55 wed_clr(dev, MTK_WED_CTRL,
56 @@ -252,15 +273,6 @@ mtk_wed_stop(struct mtk_wed_device *dev)
57 wdma_w32(dev, MTK_WDMA_INT_MASK, 0);
58 wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
59 wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
60 -
61 - wed_clr(dev, MTK_WED_GLO_CFG,
62 - MTK_WED_GLO_CFG_TX_DMA_EN |
63 - MTK_WED_GLO_CFG_RX_DMA_EN);
64 - wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
65 - MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
66 - MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
67 - wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
68 - MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
69 }
70
71 static void
72 @@ -313,7 +325,10 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
73 MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
74 wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
75
76 - wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_RX_INFO_PRERES);
77 + wdma_set(dev, MTK_WDMA_GLO_CFG,
78 + MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
79 + MTK_WDMA_GLO_CFG_RX_INFO2_PRERES |
80 + MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
81
82 offset = dev->hw->index ? 0x04000400 : 0;
83 wed_w32(dev, MTK_WED_WDMA_OFFSET0, 0x2a042a20 + offset);
84 @@ -520,43 +535,38 @@ mtk_wed_wdma_ring_setup(struct mtk_wed_d
85 }
86
87 static void
88 -mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
89 +mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask)
90 {
91 - u32 wdma_mask;
92 - u32 val;
93 - int i;
94 -
95 - for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
96 - if (!dev->tx_wdma[i].desc)
97 - mtk_wed_wdma_ring_setup(dev, i, 16);
98 -
99 - wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));
100 -
101 - mtk_wed_hw_init(dev);
102 + u32 wdma_mask = FIELD_PREP(MTK_WDMA_INT_MASK_RX_DONE, GENMASK(1, 0));
103
104 + /* wed control cr set */
105 wed_set(dev, MTK_WED_CTRL,
106 MTK_WED_CTRL_WDMA_INT_AGENT_EN |
107 MTK_WED_CTRL_WPDMA_INT_AGENT_EN |
108 MTK_WED_CTRL_WED_TX_BM_EN |
109 MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
110
111 - wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, MTK_WED_PCIE_INT_TRIGGER_STATUS);
112 + wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
113 + MTK_WED_PCIE_INT_TRIGGER_STATUS);
114
115 wed_w32(dev, MTK_WED_WPDMA_INT_TRIGGER,
116 MTK_WED_WPDMA_INT_TRIGGER_RX_DONE |
117 MTK_WED_WPDMA_INT_TRIGGER_TX_DONE);
118
119 - wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
120 - MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
121 -
122 + /* initail wdma interrupt agent */
123 wed_w32(dev, MTK_WED_WDMA_INT_TRIGGER, wdma_mask);
124 wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
125
126 wdma_w32(dev, MTK_WDMA_INT_MASK, wdma_mask);
127 wdma_w32(dev, MTK_WDMA_INT_GRP2, wdma_mask);
128 -
129 wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
130 wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
131 +}
132 +
133 +static void
134 +mtk_wed_dma_enable(struct mtk_wed_device *dev)
135 +{
136 + wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
137
138 wed_set(dev, MTK_WED_GLO_CFG,
139 MTK_WED_GLO_CFG_TX_DMA_EN |
140 @@ -567,6 +577,26 @@ mtk_wed_start(struct mtk_wed_device *dev
141 wed_set(dev, MTK_WED_WDMA_GLO_CFG,
142 MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
143
144 + wdma_set(dev, MTK_WDMA_GLO_CFG,
145 + MTK_WDMA_GLO_CFG_TX_DMA_EN |
146 + MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
147 + MTK_WDMA_GLO_CFG_RX_INFO2_PRERES |
148 + MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
149 +}
150 +
151 +static void
152 +mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
153 +{
154 + u32 val;
155 + int i;
156 +
157 + for (i = 0; i < ARRAY_SIZE(dev->tx_wdma); i++)
158 + if (!dev->tx_wdma[i].desc)
159 + mtk_wed_wdma_ring_setup(dev, i, 16);
160 +
161 + mtk_wed_hw_init(dev);
162 + mtk_wed_configure_irq(dev, irq_mask);
163 +
164 mtk_wed_set_ext_int(dev, true);
165 val = dev->wlan.wpdma_phys |
166 MTK_PCIE_MIRROR_MAP_EN |
167 @@ -577,6 +607,7 @@ mtk_wed_start(struct mtk_wed_device *dev
168 val |= BIT(0);
169 regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
170
171 + mtk_wed_dma_enable(dev);
172 dev->running = true;
173 }
174
175 --- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
176 +++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
177 @@ -224,7 +224,11 @@ struct mtk_wdma_desc {
178 #define MTK_WDMA_RING_RX(_n) (0x100 + (_n) * 0x10)
179
180 #define MTK_WDMA_GLO_CFG 0x204
181 -#define MTK_WDMA_GLO_CFG_RX_INFO_PRERES GENMASK(28, 26)
182 +#define MTK_WDMA_GLO_CFG_TX_DMA_EN BIT(0)
183 +#define MTK_WDMA_GLO_CFG_RX_DMA_EN BIT(2)
184 +#define MTK_WDMA_GLO_CFG_RX_INFO3_PRERES BIT(26)
185 +#define MTK_WDMA_GLO_CFG_RX_INFO2_PRERES BIT(27)
186 +#define MTK_WDMA_GLO_CFG_RX_INFO1_PRERES BIT(28)
187
188 #define MTK_WDMA_RESET_IDX 0x208
189 #define MTK_WDMA_RESET_IDX_TX GENMASK(3, 0)
Staging tree of Piotr Dymacz