git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From 96412158397ca0e41db1eb7cec4f51a2280d1bf1 Mon Sep 17 00:00:00 2001
   2 From: Mihai Serban <mihai.serban@nxp.com>
   3 Date: Thu, 27 Apr 2017 18:47:42 +0300
   4 Subject: [PATCH] MLK-14935: ASoC: fsl_sai: Fix mixing initialization data with
   5  actual audio samples
   6
   7 When starting a playback the initialization data used to reduce underruns
   8 was send to the transmit data register after the DMA requests were enabled.
   9 This patch moves the initialization phase before enabling the DMA so the
  10 data is transmitted in correct order.
  11
  12 Signed-off-by: Mihai Serban <mihai.serban@nxp.com>
  13 ---
  14  sound/soc/fsl/fsl_sai.c | 5 ++---
  15  1 file changed, 2 insertions(+), 3 deletions(-)
  16
  17 --- a/sound/soc/fsl/fsl_sai.c
  18 +++ b/sound/soc/fsl/fsl_sai.c
  19 @@ -594,15 +594,14 @@ static int fsl_sai_trigger(struct snd_pc
  20         case SNDRV_PCM_TRIGGER_START:
  21         case SNDRV_PCM_TRIGGER_RESUME:
  22         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  23 -               regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
  24 -                                  FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
  25 -
  26                 for (i = 0; tx && i < channels; i++)
  27                         regmap_write(sai->regmap, FSL_SAI_TDR0, 0x0);
  28                 if (tx)
  29                         udelay(10);
  30
  31                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
  32 +                                  FSL_SAI_CSR_FRDE, FSL_SAI_CSR_FRDE);
  33 +               regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
  34                                    FSL_SAI_CSR_TERE, FSL_SAI_CSR_TERE);
  35                 regmap_update_bits(sai->regmap, FSL_SAI_xCSR(tx),
  36                                    FSL_SAI_CSR_SE, FSL_SAI_CSR_SE);