git.openwrt.org Git - openwrt/staging/hauke.git/blob

   1 From 61d471c8da972c7ebbaf63779bf8100ee1ec54eb Mon Sep 17 00:00:00 2001
   2 From: Ran Wang <ran.wang_1@nxp.com>
   3 Date: Wed, 16 Jan 2019 13:23:17 +0800
   4 Subject: [PATCH] usb: dwc3: Add workaround for host mode VBUS glitch when boot
   5
   6 When DWC3 is set to host mode by programming register DWC3_GCTL, VBUS
   7 (or its control signal) will be turned on immediately on related Root Hub
   8 ports. Then, the VBUS is turned off for a little while(15us) when do xhci
   9 reset (conducted by xhci driver) and back to normal finally, we can
  10 observe a negative glitch of related signal happen.
  11
  12 This VBUS glitch might cause some USB devices enumeration fail if kernel
  13 boot with them connected. Such as LS1012AFWRY/LS1043ARDB/LX2160AQDS
  14 /LS1088ARDB with Kingston 16GB USB2.0/Kingston USB3.0/JetFlash Transcend
  15 4GB USB2.0 drives. The fail cases include enumerated as full-speed device
  16 or report wrong device descriptor, etc.
  17
  18 One SW workaround which can fix this is by programing all xhci PORTSC[PP]
  19 to 0 to turn off VBUS immediately after setting host mode in DWC3 driver
  20 (per signal measurement result, it will be too late to do it in
  21 xhci-plat.c or xhci.c). Then, after xhci reset complete in xhci driver,
  22 PORTSC[PP]s' value will back to 1 automatically and VBUS on at that time,
  23 no glitch happen and normal enumeration process has no impact.
  24
  25 Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
  26 Reviewed-by: Peter Chen <peter.chen@nxp.com>
  27 ---
  28  drivers/usb/dwc3/core.c |  3 +++
  29  drivers/usb/dwc3/core.h |  3 +++
  30  drivers/usb/dwc3/host.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
  31  3 files changed, 54 insertions(+)
  32
  33 --- a/drivers/usb/dwc3/core.c
  34 +++ b/drivers/usb/dwc3/core.c
  35 @@ -1365,6 +1365,9 @@ static void dwc3_get_properties(struct d
  36         dwc->dis_split_quirk = device_property_read_bool(dev,
  37                                 "snps,dis-split-quirk");
  38
  39 +       dwc->host_vbus_glitches = device_property_read_bool(dev,
  40 +                               "snps,host-vbus-glitches");
  41 +
  42         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  43         dwc->tx_de_emphasis = tx_de_emphasis;
  44
  45 --- a/drivers/usb/dwc3/core.h
  46 +++ b/drivers/usb/dwc3/core.h
  47 @@ -1049,6 +1049,8 @@ struct dwc3_scratchpad_array {
  48   *     3       - Reserved
  49   * @dis_metastability_quirk: set to disable metastability quirk.
  50   * @dis_split_quirk: set to disable split boundary.
  51 + * @host_vbus_glitches: set to avoid vbus glitch during
  52 + *                      xhci reset.
  53   * @imod_interval: set the interrupt moderation interval in 250ns
  54   *                 increments or 0 to disable.
  55   */
  56 @@ -1245,6 +1247,8 @@ struct dwc3 {
  57
  58         unsigned                dis_split_quirk:1;
  59
  60 +       unsigned                host_vbus_glitches:1;
  61 +
  62         u16                     imod_interval;
  63  };
  64
  65 --- a/drivers/usb/dwc3/host.c
  66 +++ b/drivers/usb/dwc3/host.c
  67 @@ -16,6 +16,44 @@ static const struct xhci_plat_priv dwc3_
  68         .quirks = XHCI_SKIP_PHY_INIT,
  69  };
  70
  71 +#define XHCI_HCSPARAMS1                0x4
  72 +#define XHCI_PORTSC_BASE       0x400
  73 +
  74 +/*
  75 + * dwc3_power_off_all_roothub_ports - Power off all Root hub ports
  76 + * @dwc3: Pointer to our controller context structure
  77 + */
  78 +static void dwc3_power_off_all_roothub_ports(struct dwc3 *dwc)
  79 +{
  80 +       int i, port_num;
  81 +       u32 reg, op_regs_base, offset;
  82 +       void __iomem *xhci_regs;
  83 +
  84 +       /* xhci regs is not mapped yet, do it temperary here */
  85 +       if (dwc->xhci_resources[0].start) {
  86 +               xhci_regs = ioremap(dwc->xhci_resources[0].start,
  87 +                               DWC3_XHCI_REGS_END);
  88 +               if (IS_ERR(xhci_regs)) {
  89 +                       dev_err(dwc->dev, "Failed to ioremap xhci_regs\n");
  90 +                       return;
  91 +               }
  92 +
  93 +               op_regs_base = HC_LENGTH(readl(xhci_regs));
  94 +               reg = readl(xhci_regs + XHCI_HCSPARAMS1);
  95 +               port_num = HCS_MAX_PORTS(reg);
  96 +
  97 +               for (i = 1; i <= port_num; i++) {
  98 +                       offset = op_regs_base + XHCI_PORTSC_BASE + 0x10*(i-1);
  99 +                       reg = readl(xhci_regs + offset);
 100 +                       reg &= ~PORT_POWER;
 101 +                       writel(reg, xhci_regs + offset);
 102 +               }
 103 +
 104 +               iounmap(xhci_regs);
 105 +       } else
 106 +               dev_err(dwc->dev, "xhci base reg invalid\n");
 107 +}
 108 +
 109  static int dwc3_host_get_irq(struct dwc3 *dwc)
 110  {
 111         struct platform_device  *dwc3_pdev = to_platform_device(dwc->dev);
 112 @@ -55,6 +93,13 @@ int dwc3_host_init(struct dwc3 *dwc)
 113         struct platform_device  *dwc3_pdev = to_platform_device(dwc->dev);
 114         int                     prop_idx = 0;
 115
 116 +       /*
 117 +        * We have to power off all Root hub ports immediately after DWC3 set
 118 +        * to host mode to avoid VBUS glitch happen when xhci get reset later.
 119 +        */
 120 +       if (dwc->host_vbus_glitches)
 121 +               dwc3_power_off_all_roothub_ports(dwc);
 122 +
 123         irq = dwc3_host_get_irq(dwc);
 124         if (irq < 0)
 125                 return irq;