git.openwrt.org Git - openwrt/staging/neocturne.git/blob

   1 Add more registers for QCA955x and QCA956x.
   2
   3 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   4 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   5 @@ -175,6 +175,35 @@
   6  /*
   7   * Hidden Registers
   8   */
   9 +#define QCA956X_MAC_CFG_BASE           0xb9000000
  10 +#define QCA956X_MAC_CFG_SIZE           0x64
  11 +
  12 +#define QCA956X_MAC_CFG1_REG           0x00
  13 +#define QCA956X_MAC_CFG1_SOFT_RST      BIT(31)
  14 +#define QCA956X_MAC_CFG1_RX_RST                BIT(19)
  15 +#define QCA956X_MAC_CFG1_TX_RST                BIT(18)
  16 +#define QCA956X_MAC_CFG1_LOOPBACK      BIT(8)
  17 +#define QCA956X_MAC_CFG1_RX_EN         BIT(2)
  18 +#define QCA956X_MAC_CFG1_TX_EN         BIT(0)
  19 +
  20 +#define QCA956X_MAC_CFG2_REG           0x04
  21 +#define QCA956X_MAC_CFG2_IF_1000       BIT(9)
  22 +#define QCA956X_MAC_CFG2_IF_10_100     BIT(8)
  23 +#define QCA956X_MAC_CFG2_HUGE_FRAME_EN BIT(5)
  24 +#define QCA956X_MAC_CFG2_LEN_CHECK     BIT(4)
  25 +#define QCA956X_MAC_CFG2_PAD_CRC_EN    BIT(2)
  26 +#define QCA956X_MAC_CFG2_FDX           BIT(0)
  27 +
  28 +#define QCA956X_MAC_MII_MGMT_CFG_REG   0x20
  29 +#define QCA956X_MGMT_CFG_CLK_DIV_20    0x07
  30 +
  31 +#define QCA956X_MAC_FIFO_CFG0_REG      0x48
  32 +#define QCA956X_MAC_FIFO_CFG1_REG      0x4c
  33 +#define QCA956X_MAC_FIFO_CFG2_REG      0x50
  34 +#define QCA956X_MAC_FIFO_CFG3_REG      0x54
  35 +#define QCA956X_MAC_FIFO_CFG4_REG      0x58
  36 +#define QCA956X_MAC_FIFO_CFG5_REG      0x5c
  37 +
  38  #define QCA956X_DAM_RESET_OFFSET       0xb90001bc
  39  #define QCA956X_DAM_RESET_SIZE         0x4
  40  #define QCA956X_INLINE_CHKSUM_ENG      BIT(27)
  41 @@ -384,6 +413,7 @@
  42  #define QCA955X_PLL_CLK_CTRL_REG               0x08
  43  #define QCA955X_PLL_ETH_XMII_CONTROL_REG       0x28
  44  #define QCA955X_PLL_ETH_SGMII_CONTROL_REG      0x48
  45 +#define QCA955X_PLL_ETH_SGMII_SERDES_REG       0x4c
  46
  47  #define QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT     0
  48  #define QCA955X_PLL_CPU_CONFIG_NFRAC_MASK      0x3f
  49 @@ -416,12 +446,18 @@
  50  #define QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL                BIT(21)
  51  #define QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
  52
  53 +#define QCA955X_PLL_ETH_SGMII_SERDES_LOCK_DETECT       BIT(2)
  54 +#define QCA955X_PLL_ETH_SGMII_SERDES_PLL_REFCLK                BIT(1)
  55 +#define QCA955X_PLL_ETH_SGMII_SERDES_EN_PLL            BIT(0)
  56 +
  57  #define QCA956X_PLL_CPU_CONFIG_REG                     0x00
  58  #define QCA956X_PLL_CPU_CONFIG1_REG                    0x04
  59  #define QCA956X_PLL_DDR_CONFIG_REG                     0x08
  60  #define QCA956X_PLL_DDR_CONFIG1_REG                    0x0c
  61  #define QCA956X_PLL_CLK_CTRL_REG                       0x10
  62 +#define QCA956X_PLL_SWITCH_CLOCK_CONTROL_REG           0x28
  63  #define QCA956X_PLL_ETH_XMII_CONTROL_REG               0x30
  64 +#define QCA956X_PLL_ETH_SGMII_SERDES_REG               0x4c
  65
  66  #define QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT            12
  67  #define QCA956X_PLL_CPU_CONFIG_REFDIV_MASK             0x1f
  68 @@ -460,6 +496,31 @@
  69  #define QCA956X_PLL_CLK_CTRL_CPU_DDRCLK_FROM_CPUPLL    BIT(21)
  70  #define QCA956X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL                BIT(24)
  71
  72 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_I2C_CLK_SELB            BIT(5)
  73 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_1         BIT(6)
  74 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_UART1_CLK_SEL           BIT(7)
  75 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_SHIFT 8
  76 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_USB_REFCLK_FREQ_SEL_MASK         0xf
  77 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EN_PLL_TOP              BIT(12)
  78 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL0_2         BIT(13)
  79 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_1         BIT(14)
  80 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_MDIO_CLK_SEL1_2         BIT(15)
  81 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCH_FUNC_TST_MODE    BIT(16)
  82 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_EEE_ENABLE              BIT(17)
  83 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_OEN_CLK125M_PLL         BIT(18)
  84 +#define QCA956X_PLL_SWITCH_CLOCK_SPARE_SWITCHCLK_SEL           BIT(19)
  85 +
  86 +#define QCA956X_PLL_ETH_XMII_TX_INVERT                 BIT(1)
  87 +#define QCA956X_PLL_ETH_XMII_GIGE                      BIT(25)
  88 +#define QCA956X_PLL_ETH_XMII_RX_DELAY_SHIFT            28
  89 +#define QCA956X_PLL_ETH_XMII_RX_DELAY_MASK             0x3
  90 +#define QCA956X_PLL_ETH_XMII_TX_DELAY_SHIFT            26
  91 +#define QCA956X_PLL_ETH_XMII_TX_DELAY_MASK             3
  92 +
  93 +#define QCA956X_PLL_ETH_SGMII_SERDES_LOCK_DETECT               BIT(2)
  94 +#define QCA956X_PLL_ETH_SGMII_SERDES_PLL_REFCLK                        BIT(1)
  95 +#define QCA956X_PLL_ETH_SGMII_SERDES_EN_PLL                    BIT(0)
  96 +
  97  /*
  98   * USB_CONFIG block
  99   */
 100 @@ -657,6 +718,25 @@
 101  #define QCA955X_RESET_MBOX             BIT(1)
 102  #define QCA955X_RESET_I2S              BIT(0)
 103
 104 +#define QCA956X_RESET_EXTERNAL         BIT(28)
 105 +#define QCA956X_RESET_FULL_CHIP                BIT(24)
 106 +#define QCA956X_RESET_GE1_MDIO         BIT(23)
 107 +#define QCA956X_RESET_GE0_MDIO         BIT(22)
 108 +#define QCA956X_RESET_CPU_NMI          BIT(21)
 109 +#define QCA956X_RESET_CPU_COLD         BIT(20)
 110 +#define QCA956X_RESET_DMA              BIT(19)
 111 +#define QCA956X_RESET_DDR              BIT(16)
 112 +#define QCA956X_RESET_GE1_MAC          BIT(13)
 113 +#define QCA956X_RESET_SGMII_ANALOG     BIT(12)
 114 +#define QCA956X_RESET_USB_PHY_ANALOG   BIT(11)
 115 +#define QCA956X_RESET_GE0_MAC          BIT(9)
 116 +#define QCA956X_RESET_SGMII            BIT(8)
 117 +#define QCA956X_RESET_USB_HOST         BIT(5)
 118 +#define QCA956X_RESET_USB_PHY          BIT(4)
 119 +#define QCA956X_RESET_USBSUS_OVERRIDE  BIT(3)
 120 +#define QCA956X_RESET_SWITCH_ANALOG    BIT(2)
 121 +#define QCA956X_RESET_SWITCH           BIT(0)
 122 +
 123  #define AR933X_BOOTSTRAP_MDIO_GPIO_EN  BIT(18)
 124  #define AR933X_BOOTSTRAP_EEPBUSY       BIT(4)
 125  #define AR933X_BOOTSTRAP_USB_MODE_HOST BIT(3)
 126 @@ -1189,6 +1269,7 @@
 127   */
 128
 129  #define QCA955X_GMAC_REG_ETH_CFG       0x00
 130 +#define QCA955X_GMAC_REG_SGMII_SERDES  0x18
 131
 132  #define QCA955X_ETH_CFG_RGMII_EN       BIT(0)
 133  #define QCA955X_ETH_CFG_MII_GE0                BIT(1)
 134 @@ -1210,16 +1291,58 @@
 135  #define QCA955X_ETH_CFG_TXE_DELAY_MASK 0x3
 136  #define QCA955X_ETH_CFG_TXE_DELAY_SHIFT        20
 137
 138 +#define QCA955X_SGMII_SERDES_LOCK_DETECT_STATUS        BIT(15)
 139 +#define QCA955X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
 140 +#define QCA955X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
 141  /*
 142   * QCA956X GMAC Interface
 143   */
 144
 145 -#define QCA956X_GMAC_REG_ETH_CFG               0x00
 146 +#define QCA956X_GMAC_REG_ETH_CFG       0x00
 147 +#define QCA956X_GMAC_REG_SGMII_RESET   0x14
 148 +#define QCA956X_GMAC_REG_SGMII_SERDES  0x18
 149 +#define QCA956X_GMAC_REG_MR_AN_CONTROL 0x1c
 150 +#define QCA956X_GMAC_REG_SGMII_CONFIG  0x34
 151 +#define QCA956X_GMAC_REG_SGMII_DEBUG   0x58
 152
 153 +#define QCA956X_ETH_CFG_RGMII_EN               BIT(0)
 154 +#define QCA956X_ETH_CFG_GE0_SGMII              BIT(6)
 155  #define QCA956X_ETH_CFG_SW_ONLY_MODE           BIT(7)
 156 -#define QCA956X_ETH_CFG_SW_PHY_SWAP                BIT(8)
 157 +#define QCA956X_ETH_CFG_SW_PHY_SWAP            BIT(8)
 158  #define QCA956X_ETH_CFG_SW_PHY_ADDR_SWAP       BIT(9)
 159  #define QCA956X_ETH_CFG_SW_APB_ACCESS          BIT(10)
 160  #define QCA956X_ETH_CFG_SW_ACC_MSB_FIRST       BIT(13)
 161 +#define QCA956X_ETH_CFG_RXD_DELAY_MASK         0x3
 162 +#define QCA956X_ETH_CFG_RXD_DELAY_SHIFT                14
 163 +#define QCA956X_ETH_CFG_RDV_DELAY_MASK         0x3
 164 +#define QCA956X_ETH_CFG_RDV_DELAY_SHIFT                16
 165 +
 166 +#define QCA956X_SGMII_RESET_RX_CLK_N_RESET     0x0
 167 +#define QCA956X_SGMII_RESET_RX_CLK_N           BIT(0)
 168 +#define QCA956X_SGMII_RESET_TX_CLK_N           BIT(1)
 169 +#define QCA956X_SGMII_RESET_RX_125M_N          BIT(2)
 170 +#define QCA956X_SGMII_RESET_TX_125M_N          BIT(3)
 171 +#define QCA956X_SGMII_RESET_HW_RX_125M_N       BIT(4)
 172 +
 173 +#define QCA956X_SGMII_SERDES_CDR_BW_MASK       0x3
 174 +#define QCA956X_SGMII_SERDES_CDR_BW_SHIFT      1
 175 +#define QCA956X_SGMII_SERDES_TX_DR_CTRL_MASK   0x7
 176 +#define QCA956X_SGMII_SERDES_TX_DR_CTRL_SHIFT  4
 177 +#define QCA956X_SGMII_SERDES_PLL_BW            BIT(8)
 178 +#define QCA956X_SGMII_SERDES_VCO_FAST          BIT(9)
 179 +#define QCA956X_SGMII_SERDES_VCO_SLOW          BIT(10)
 180 +#define QCA956X_SGMII_SERDES_LOCK_DETECT_STATUS        BIT(15)
 181 +#define QCA956X_SGMII_SERDES_EN_SIGNAL_DETECT  BIT(16)
 182 +#define QCA956X_SGMII_SERDES_FIBER_SDO         BIT(17)
 183 +#define QCA956X_SGMII_SERDES_RES_CALIBRATION_SHIFT 23
 184 +#define QCA956X_SGMII_SERDES_RES_CALIBRATION_MASK 0xf
 185 +#define QCA956X_SGMII_SERDES_VCO_REG_SHIFT     27
 186 +#define QCA956X_SGMII_SERDES_VCO_REG_MASK      0xf
 187 +
 188 +#define QCA956X_MR_AN_CONTROL_AN_ENABLE                BIT(12)
 189 +#define QCA956X_MR_AN_CONTROL_PHY_RESET                BIT(15)
 190 +
 191 +#define QCA956X_SGMII_CONFIG_MODE_CTRL_SHIFT   0
 192 +#define QCA956X_SGMII_CONFIG_MODE_CTRL_MASK    0x7
 193
 194  #endif /* __ASM_MACH_AR71XX_REGS_H */