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1 From 90ae68bfc2ffcb54a4ba4f64edbeb84a80cbb57c Mon Sep 17 00:00:00 2001
2 From: Ansuel Smith <ansuelsmth@gmail.com>
3 Date: Mon, 22 Nov 2021 16:23:41 +0100
4 Subject: net: dsa: qca8k: convert to GENMASK/FIELD_PREP/FIELD_GET
5
6 Convert and try to standardize bit fields using
7 GENMASK/FIELD_PREP/FIELD_GET macros. Rework some logic to support the
8 standard macro and tidy things up. No functional change intended.
9
10 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
11 Signed-off-by: David S. Miller <davem@davemloft.net>
12 ---
13 drivers/net/dsa/qca8k.c | 98 +++++++++++++++----------------
14 drivers/net/dsa/qca8k.h | 153 ++++++++++++++++++++++++++----------------------
15 2 files changed, 130 insertions(+), 121 deletions(-)
16
17 diff --git a/drivers/net/dsa/qca8k.c b/drivers/net/dsa/qca8k.c
18 index bfffc1fb7016d..0eceb9cba2dc8 100644
19 --- a/drivers/net/dsa/qca8k.c
20 +++ b/drivers/net/dsa/qca8k.c
21 @@ -9,6 +9,7 @@
22 #include <linux/module.h>
23 #include <linux/phy.h>
24 #include <linux/netdevice.h>
25 +#include <linux/bitfield.h>
26 #include <net/dsa.h>
27 #include <linux/of_net.h>
28 #include <linux/of_mdio.h>
29 @@ -319,18 +320,18 @@ qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
30 }
31
32 /* vid - 83:72 */
33 - fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
34 + fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);
35 /* aging - 67:64 */
36 - fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
37 + fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]);
38 /* portmask - 54:48 */
39 - fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
40 + fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]);
41 /* mac - 47:0 */
42 - fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
43 - fdb->mac[1] = reg[1] & 0xff;
44 - fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
45 - fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
46 - fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
47 - fdb->mac[5] = reg[0] & 0xff;
48 + fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]);
49 + fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]);
50 + fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]);
51 + fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]);
52 + fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]);
53 + fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]);
54
55 return 0;
56 }
57 @@ -343,18 +344,18 @@ qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
58 int i;
59
60 /* vid - 83:72 */
61 - reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
62 + reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);
63 /* aging - 67:64 */
64 - reg[2] |= aging & QCA8K_ATU_STATUS_M;
65 + reg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging);
66 /* portmask - 54:48 */
67 - reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
68 + reg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask);
69 /* mac - 47:0 */
70 - reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
71 - reg[1] |= mac[1];
72 - reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
73 - reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
74 - reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
75 - reg[0] |= mac[5];
76 + reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]);
77 + reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]);
78 + reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]);
79 + reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]);
80 + reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]);
81 + reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);
82
83 /* load the array into the ARL table */
84 for (i = 0; i < 3; i++)
85 @@ -372,7 +373,7 @@ qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
86 reg |= cmd;
87 if (port >= 0) {
88 reg |= QCA8K_ATU_FUNC_PORT_EN;
89 - reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
90 + reg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port);
91 }
92
93 /* Write the function register triggering the table access */
94 @@ -454,7 +455,7 @@ qca8k_vlan_access(struct qca8k_priv *priv, enum qca8k_vlan_cmd cmd, u16 vid)
95 /* Set the command and VLAN index */
96 reg = QCA8K_VTU_FUNC1_BUSY;
97 reg |= cmd;
98 - reg |= vid << QCA8K_VTU_FUNC1_VID_S;
99 + reg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid);
100
101 /* Write the function register triggering the table access */
102 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
103 @@ -500,13 +501,11 @@ qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid, bool untagged)
104 if (ret < 0)
105 goto out;
106 reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
107 - reg &= ~(QCA8K_VTU_FUNC0_EG_MODE_MASK << QCA8K_VTU_FUNC0_EG_MODE_S(port));
108 + reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
109 if (untagged)
110 - reg |= QCA8K_VTU_FUNC0_EG_MODE_UNTAG <<
111 - QCA8K_VTU_FUNC0_EG_MODE_S(port);
112 + reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port);
113 else
114 - reg |= QCA8K_VTU_FUNC0_EG_MODE_TAG <<
115 - QCA8K_VTU_FUNC0_EG_MODE_S(port);
116 + reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port);
117
118 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
119 if (ret)
120 @@ -534,15 +533,13 @@ qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
121 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, &reg);
122 if (ret < 0)
123 goto out;
124 - reg &= ~(3 << QCA8K_VTU_FUNC0_EG_MODE_S(port));
125 - reg |= QCA8K_VTU_FUNC0_EG_MODE_NOT <<
126 - QCA8K_VTU_FUNC0_EG_MODE_S(port);
127 + reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
128 + reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port);
129
130 /* Check if we're the last member to be removed */
131 del = true;
132 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
133 - mask = QCA8K_VTU_FUNC0_EG_MODE_NOT;
134 - mask <<= QCA8K_VTU_FUNC0_EG_MODE_S(i);
135 + mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
136
137 if ((reg & mask) != mask) {
138 del = false;
139 @@ -1014,7 +1011,7 @@ qca8k_parse_port_config(struct qca8k_priv *priv)
140 mode == PHY_INTERFACE_MODE_RGMII_TXID)
141 delay = 1;
142
143 - if (delay > QCA8K_MAX_DELAY) {
144 + if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, delay)) {
145 dev_err(priv->dev, "rgmii tx delay is limited to a max value of 3ns, setting to the max value");
146 delay = 3;
147 }
148 @@ -1030,7 +1027,7 @@ qca8k_parse_port_config(struct qca8k_priv *priv)
149 mode == PHY_INTERFACE_MODE_RGMII_RXID)
150 delay = 2;
151
152 - if (delay > QCA8K_MAX_DELAY) {
153 + if (!FIELD_FIT(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, delay)) {
154 dev_err(priv->dev, "rgmii rx delay is limited to a max value of 3ns, setting to the max value");
155 delay = 3;
156 }
157 @@ -1141,8 +1138,8 @@ qca8k_setup(struct dsa_switch *ds)
158 /* Enable QCA header mode on all cpu ports */
159 if (dsa_is_cpu_port(ds, i)) {
160 ret = qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(i),
161 - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
162 - QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
163 + FIELD_PREP(QCA8K_PORT_HDR_CTRL_TX_MASK, QCA8K_PORT_HDR_CTRL_ALL) |
164 + FIELD_PREP(QCA8K_PORT_HDR_CTRL_RX_MASK, QCA8K_PORT_HDR_CTRL_ALL));
165 if (ret) {
166 dev_err(priv->dev, "failed enabling QCA header mode");
167 return ret;
168 @@ -1159,10 +1156,10 @@ qca8k_setup(struct dsa_switch *ds)
169 * for igmp, unknown, multicast and broadcast packet
170 */
171 ret = qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
172 - BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
173 - BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
174 - BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
175 - BIT(cpu_port) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
176 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK, BIT(cpu_port)) |
177 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK, BIT(cpu_port)) |
178 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK, BIT(cpu_port)) |
179 + FIELD_PREP(QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK, BIT(cpu_port)));
180 if (ret)
181 return ret;
182
183 @@ -1180,8 +1177,6 @@ qca8k_setup(struct dsa_switch *ds)
184
185 /* Individual user ports get connected to CPU port only */
186 if (dsa_is_user_port(ds, i)) {
187 - int shift = 16 * (i % 2);
188 -
189 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
190 QCA8K_PORT_LOOKUP_MEMBER,
191 BIT(cpu_port));
192 @@ -1198,8 +1193,8 @@ qca8k_setup(struct dsa_switch *ds)
193 * default egress vid
194 */
195 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
196 - 0xfff << shift,
197 - QCA8K_PORT_VID_DEF << shift);
198 + QCA8K_EGREES_VLAN_PORT_MASK(i),
199 + QCA8K_EGREES_VLAN_PORT(i, QCA8K_PORT_VID_DEF));
200 if (ret)
201 return ret;
202
203 @@ -1246,7 +1241,7 @@ qca8k_setup(struct dsa_switch *ds)
204 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
205 QCA8K_PORT_HOL_CTRL1_WRED_EN;
206 qca8k_rmw(priv, QCA8K_REG_PORT_HOL_CTRL1(i),
207 - QCA8K_PORT_HOL_CTRL1_ING_BUF |
208 + QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK |
209 QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN |
210 QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN |
211 QCA8K_PORT_HOL_CTRL1_WRED_EN,
212 @@ -1265,8 +1260,8 @@ qca8k_setup(struct dsa_switch *ds)
213 mask = QCA8K_GLOBAL_FC_GOL_XON_THRES(288) |
214 QCA8K_GLOBAL_FC_GOL_XOFF_THRES(496);
215 qca8k_rmw(priv, QCA8K_REG_GLOBAL_FC_THRESH,
216 - QCA8K_GLOBAL_FC_GOL_XON_THRES_S |
217 - QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S,
218 + QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK |
219 + QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK,
220 mask);
221 }
222
223 @@ -1912,11 +1907,11 @@ qca8k_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering,
224
225 if (vlan_filtering) {
226 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
227 - QCA8K_PORT_LOOKUP_VLAN_MODE,
228 + QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
229 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
230 } else {
231 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
232 - QCA8K_PORT_LOOKUP_VLAN_MODE,
233 + QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
234 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
235 }
236
237 @@ -1940,10 +1935,9 @@ qca8k_port_vlan_add(struct dsa_switch *ds, int port,
238 }
239
240 if (pvid) {
241 - int shift = 16 * (port % 2);
242 -
243 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
244 - 0xfff << shift, vlan->vid << shift);
245 + QCA8K_EGREES_VLAN_PORT_MASK(port),
246 + QCA8K_EGREES_VLAN_PORT(port, vlan->vid));
247 if (ret)
248 return ret;
249
250 @@ -2037,7 +2031,7 @@ static int qca8k_read_switch_id(struct qca8k_priv *priv)
251 if (ret < 0)
252 return -ENODEV;
253
254 - id = QCA8K_MASK_CTRL_DEVICE_ID(val & QCA8K_MASK_CTRL_DEVICE_ID_MASK);
255 + id = QCA8K_MASK_CTRL_DEVICE_ID(val);
256 if (id != data->id) {
257 dev_err(priv->dev, "Switch id detected %x but expected %x", id, data->id);
258 return -ENODEV;
259 @@ -2046,7 +2040,7 @@ static int qca8k_read_switch_id(struct qca8k_priv *priv)
260 priv->switch_id = id;
261
262 /* Save revision to communicate to the internal PHY driver */
263 - priv->switch_revision = (val & QCA8K_MASK_CTRL_REV_ID_MASK);
264 + priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val);
265
266 return 0;
267 }
268 diff --git a/drivers/net/dsa/qca8k.h b/drivers/net/dsa/qca8k.h
269 index 128b8cf85e080..085885275398b 100644
270 --- a/drivers/net/dsa/qca8k.h
271 +++ b/drivers/net/dsa/qca8k.h
272 @@ -30,9 +30,9 @@
273 /* Global control registers */
274 #define QCA8K_REG_MASK_CTRL 0x000
275 #define QCA8K_MASK_CTRL_REV_ID_MASK GENMASK(7, 0)
276 -#define QCA8K_MASK_CTRL_REV_ID(x) ((x) >> 0)
277 +#define QCA8K_MASK_CTRL_REV_ID(x) FIELD_GET(QCA8K_MASK_CTRL_REV_ID_MASK, x)
278 #define QCA8K_MASK_CTRL_DEVICE_ID_MASK GENMASK(15, 8)
279 -#define QCA8K_MASK_CTRL_DEVICE_ID(x) ((x) >> 8)
280 +#define QCA8K_MASK_CTRL_DEVICE_ID(x) FIELD_GET(QCA8K_MASK_CTRL_DEVICE_ID_MASK, x)
281 #define QCA8K_REG_PORT0_PAD_CTRL 0x004
282 #define QCA8K_PORT0_PAD_MAC06_EXCHANGE_EN BIT(31)
283 #define QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE BIT(19)
284 @@ -41,12 +41,11 @@
285 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c
286 #define QCA8K_PORT_PAD_RGMII_EN BIT(26)
287 #define QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK GENMASK(23, 22)
288 -#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) ((x) << 22)
289 +#define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_TX_DELAY_MASK, x)
290 #define QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK GENMASK(21, 20)
291 -#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) ((x) << 20)
292 +#define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) FIELD_PREP(QCA8K_PORT_PAD_RGMII_RX_DELAY_MASK, x)
293 #define QCA8K_PORT_PAD_RGMII_TX_DELAY_EN BIT(25)
294 #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
295 -#define QCA8K_MAX_DELAY 3
296 #define QCA8K_PORT_PAD_SGMII_EN BIT(7)
297 #define QCA8K_REG_PWS 0x010
298 #define QCA8K_PWS_POWER_ON_SEL BIT(31)
299 @@ -68,10 +67,12 @@
300 #define QCA8K_MDIO_MASTER_READ BIT(27)
301 #define QCA8K_MDIO_MASTER_WRITE 0
302 #define QCA8K_MDIO_MASTER_SUP_PRE BIT(26)
303 -#define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21)
304 -#define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16)
305 -#define QCA8K_MDIO_MASTER_DATA(x) (x)
306 +#define QCA8K_MDIO_MASTER_PHY_ADDR_MASK GENMASK(25, 21)
307 +#define QCA8K_MDIO_MASTER_PHY_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_PHY_ADDR_MASK, x)
308 +#define QCA8K_MDIO_MASTER_REG_ADDR_MASK GENMASK(20, 16)
309 +#define QCA8K_MDIO_MASTER_REG_ADDR(x) FIELD_PREP(QCA8K_MDIO_MASTER_REG_ADDR_MASK, x)
310 #define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
311 +#define QCA8K_MDIO_MASTER_DATA(x) FIELD_PREP(QCA8K_MDIO_MASTER_DATA_MASK, x)
312 #define QCA8K_MDIO_MASTER_MAX_PORTS 5
313 #define QCA8K_MDIO_MASTER_MAX_REG 32
314 #define QCA8K_GOL_MAC_ADDR0 0x60
315 @@ -93,9 +94,7 @@
316 #define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
317 #define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
318 #define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
319 -#define QCA8K_PORT_HDR_CTRL_RX_S 2
320 #define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
321 -#define QCA8K_PORT_HDR_CTRL_TX_S 0
322 #define QCA8K_PORT_HDR_CTRL_ALL 2
323 #define QCA8K_PORT_HDR_CTRL_MGMT 1
324 #define QCA8K_PORT_HDR_CTRL_NONE 0
325 @@ -105,10 +104,11 @@
326 #define QCA8K_SGMII_EN_TX BIT(3)
327 #define QCA8K_SGMII_EN_SD BIT(4)
328 #define QCA8K_SGMII_CLK125M_DELAY BIT(7)
329 -#define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23))
330 -#define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
331 -#define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
332 -#define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
333 +#define QCA8K_SGMII_MODE_CTRL_MASK GENMASK(23, 22)
334 +#define QCA8K_SGMII_MODE_CTRL(x) FIELD_PREP(QCA8K_SGMII_MODE_CTRL_MASK, x)
335 +#define QCA8K_SGMII_MODE_CTRL_BASEX QCA8K_SGMII_MODE_CTRL(0x0)
336 +#define QCA8K_SGMII_MODE_CTRL_PHY QCA8K_SGMII_MODE_CTRL(0x1)
337 +#define QCA8K_SGMII_MODE_CTRL_MAC QCA8K_SGMII_MODE_CTRL(0x2)
338
339 /* MAC_PWR_SEL registers */
340 #define QCA8K_REG_MAC_PWR_SEL 0x0e4
341 @@ -121,100 +121,115 @@
342
343 /* ACL registers */
344 #define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
345 -#define QCA8K_PORT_VLAN_CVID(x) (x << 16)
346 -#define QCA8K_PORT_VLAN_SVID(x) x
347 +#define QCA8K_PORT_VLAN_CVID_MASK GENMASK(27, 16)
348 +#define QCA8K_PORT_VLAN_CVID(x) FIELD_PREP(QCA8K_PORT_VLAN_CVID_MASK, x)
349 +#define QCA8K_PORT_VLAN_SVID_MASK GENMASK(11, 0)
350 +#define QCA8K_PORT_VLAN_SVID(x) FIELD_PREP(QCA8K_PORT_VLAN_SVID_MASK, x)
351 #define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
352 #define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
353 #define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
354
355 /* Lookup registers */
356 #define QCA8K_REG_ATU_DATA0 0x600
357 -#define QCA8K_ATU_ADDR2_S 24
358 -#define QCA8K_ATU_ADDR3_S 16
359 -#define QCA8K_ATU_ADDR4_S 8
360 +#define QCA8K_ATU_ADDR2_MASK GENMASK(31, 24)
361 +#define QCA8K_ATU_ADDR3_MASK GENMASK(23, 16)
362 +#define QCA8K_ATU_ADDR4_MASK GENMASK(15, 8)
363 +#define QCA8K_ATU_ADDR5_MASK GENMASK(7, 0)
364 #define QCA8K_REG_ATU_DATA1 0x604
365 -#define QCA8K_ATU_PORT_M 0x7f
366 -#define QCA8K_ATU_PORT_S 16
367 -#define QCA8K_ATU_ADDR0_S 8
368 +#define QCA8K_ATU_PORT_MASK GENMASK(22, 16)
369 +#define QCA8K_ATU_ADDR0_MASK GENMASK(15, 8)
370 +#define QCA8K_ATU_ADDR1_MASK GENMASK(7, 0)
371 #define QCA8K_REG_ATU_DATA2 0x608
372 -#define QCA8K_ATU_VID_M 0xfff
373 -#define QCA8K_ATU_VID_S 8
374 -#define QCA8K_ATU_STATUS_M 0xf
375 +#define QCA8K_ATU_VID_MASK GENMASK(19, 8)
376 +#define QCA8K_ATU_STATUS_MASK GENMASK(3, 0)
377 #define QCA8K_ATU_STATUS_STATIC 0xf
378 #define QCA8K_REG_ATU_FUNC 0x60c
379 #define QCA8K_ATU_FUNC_BUSY BIT(31)
380 #define QCA8K_ATU_FUNC_PORT_EN BIT(14)
381 #define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
382 #define QCA8K_ATU_FUNC_FULL BIT(12)
383 -#define QCA8K_ATU_FUNC_PORT_M 0xf
384 -#define QCA8K_ATU_FUNC_PORT_S 8
385 +#define QCA8K_ATU_FUNC_PORT_MASK GENMASK(11, 8)
386 #define QCA8K_REG_VTU_FUNC0 0x610
387 #define QCA8K_VTU_FUNC0_VALID BIT(20)
388 #define QCA8K_VTU_FUNC0_IVL_EN BIT(19)
389 -#define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
390 -#define QCA8K_VTU_FUNC0_EG_MODE_MASK 3
391 -#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0
392 -#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1
393 -#define QCA8K_VTU_FUNC0_EG_MODE_TAG 2
394 -#define QCA8K_VTU_FUNC0_EG_MODE_NOT 3
395 +/* QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(17, 4)
396 + * It does contain VLAN_MODE for each port [5:4] for port0,
397 + * [7:6] for port1 ... [17:16] for port6. Use virtual port
398 + * define to handle this.
399 + */
400 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i) (4 + (_i) * 2)
401 +#define QCA8K_VTU_FUNC0_EG_MODE_MASK GENMASK(1, 0)
402 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(_i) (GENMASK(1, 0) << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
403 +#define QCA8K_VTU_FUNC0_EG_MODE_UNMOD FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x0)
404 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNMOD(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNMOD << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
405 +#define QCA8K_VTU_FUNC0_EG_MODE_UNTAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x1)
406 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_UNTAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
407 +#define QCA8K_VTU_FUNC0_EG_MODE_TAG FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x2)
408 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(_i) (QCA8K_VTU_FUNC0_EG_MODE_TAG << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
409 +#define QCA8K_VTU_FUNC0_EG_MODE_NOT FIELD_PREP(QCA8K_VTU_FUNC0_EG_MODE_MASK, 0x3)
410 +#define QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(_i) (QCA8K_VTU_FUNC0_EG_MODE_NOT << QCA8K_VTU_FUNC0_EG_MODE_PORT_SHIFT(_i))
411 #define QCA8K_REG_VTU_FUNC1 0x614
412 #define QCA8K_VTU_FUNC1_BUSY BIT(31)
413 -#define QCA8K_VTU_FUNC1_VID_S 16
414 +#define QCA8K_VTU_FUNC1_VID_MASK GENMASK(27, 16)
415 #define QCA8K_VTU_FUNC1_FULL BIT(4)
416 #define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
417 #define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
418 #define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
419 -#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24
420 -#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16
421 -#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8
422 -#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
423 +#define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_MASK GENMASK(30, 24)
424 +#define QCA8K_GLOBAL_FW_CTRL1_BC_DP_MASK GENMASK(22, 16)
425 +#define QCA8K_GLOBAL_FW_CTRL1_MC_DP_MASK GENMASK(14, 8)
426 +#define QCA8K_GLOBAL_FW_CTRL1_UC_DP_MASK GENMASK(6, 0)
427 #define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
428 #define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
429 -#define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8)
430 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8)
431 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8)
432 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8)
433 -#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8)
434 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_MASK GENMASK(9, 8)
435 +#define QCA8K_PORT_LOOKUP_VLAN_MODE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_VLAN_MODE_MASK, x)
436 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE QCA8K_PORT_LOOKUP_VLAN_MODE(0x0)
437 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK QCA8K_PORT_LOOKUP_VLAN_MODE(0x1)
438 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK QCA8K_PORT_LOOKUP_VLAN_MODE(0x2)
439 +#define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE QCA8K_PORT_LOOKUP_VLAN_MODE(0x3)
440 #define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
441 -#define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
442 -#define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16)
443 -#define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16)
444 -#define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16)
445 -#define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16)
446 -#define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
447 +#define QCA8K_PORT_LOOKUP_STATE(x) FIELD_PREP(QCA8K_PORT_LOOKUP_STATE_MASK, x)
448 +#define QCA8K_PORT_LOOKUP_STATE_DISABLED QCA8K_PORT_LOOKUP_STATE(0x0)
449 +#define QCA8K_PORT_LOOKUP_STATE_BLOCKING QCA8K_PORT_LOOKUP_STATE(0x1)
450 +#define QCA8K_PORT_LOOKUP_STATE_LISTENING QCA8K_PORT_LOOKUP_STATE(0x2)
451 +#define QCA8K_PORT_LOOKUP_STATE_LEARNING QCA8K_PORT_LOOKUP_STATE(0x3)
452 +#define QCA8K_PORT_LOOKUP_STATE_FORWARD QCA8K_PORT_LOOKUP_STATE(0x4)
453 #define QCA8K_PORT_LOOKUP_LEARN BIT(20)
454
455 #define QCA8K_REG_GLOBAL_FC_THRESH 0x800
456 -#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) ((x) << 16)
457 -#define QCA8K_GLOBAL_FC_GOL_XON_THRES_S GENMASK(24, 16)
458 -#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) ((x) << 0)
459 -#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_S GENMASK(8, 0)
460 +#define QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK GENMASK(24, 16)
461 +#define QCA8K_GLOBAL_FC_GOL_XON_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XON_THRES_MASK, x)
462 +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK GENMASK(8, 0)
463 +#define QCA8K_GLOBAL_FC_GOL_XOFF_THRES(x) FIELD_PREP(QCA8K_GLOBAL_FC_GOL_XOFF_THRES_MASK, x)
464
465 #define QCA8K_REG_PORT_HOL_CTRL0(_i) (0x970 + (_i) * 0x8)
466 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF GENMASK(3, 0)
467 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) ((x) << 0)
468 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF GENMASK(7, 4)
469 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) ((x) << 4)
470 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF GENMASK(11, 8)
471 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) ((x) << 8)
472 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF GENMASK(15, 12)
473 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) ((x) << 12)
474 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF GENMASK(19, 16)
475 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) ((x) << 16)
476 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF GENMASK(23, 20)
477 -#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) ((x) << 20)
478 -#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF GENMASK(29, 24)
479 -#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) ((x) << 24)
480 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK GENMASK(3, 0)
481 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI0(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI0_BUF_MASK, x)
482 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK GENMASK(7, 4)
483 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI1(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI1_BUF_MASK, x)
484 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK GENMASK(11, 8)
485 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI2(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI2_BUF_MASK, x)
486 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK GENMASK(15, 12)
487 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI3(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI3_BUF_MASK, x)
488 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK GENMASK(19, 16)
489 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI4(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI4_BUF_MASK, x)
490 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK GENMASK(23, 20)
491 +#define QCA8K_PORT_HOL_CTRL0_EG_PRI5(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PRI5_BUF_MASK, x)
492 +#define QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK GENMASK(29, 24)
493 +#define QCA8K_PORT_HOL_CTRL0_EG_PORT(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL0_EG_PORT_BUF_MASK, x)
494
495 #define QCA8K_REG_PORT_HOL_CTRL1(_i) (0x974 + (_i) * 0x8)
496 -#define QCA8K_PORT_HOL_CTRL1_ING_BUF GENMASK(3, 0)
497 -#define QCA8K_PORT_HOL_CTRL1_ING(x) ((x) << 0)
498 +#define QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK GENMASK(3, 0)
499 +#define QCA8K_PORT_HOL_CTRL1_ING(x) FIELD_PREP(QCA8K_PORT_HOL_CTRL1_ING_BUF_MASK, x)
500 #define QCA8K_PORT_HOL_CTRL1_EG_PRI_BUF_EN BIT(6)
501 #define QCA8K_PORT_HOL_CTRL1_EG_PORT_BUF_EN BIT(7)
502 #define QCA8K_PORT_HOL_CTRL1_WRED_EN BIT(8)
503 #define QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN BIT(16)
504
505 /* Pkt edit registers */
506 +#define QCA8K_EGREES_VLAN_PORT_SHIFT(_i) (16 * ((_i) % 2))
507 +#define QCA8K_EGREES_VLAN_PORT_MASK(_i) (GENMASK(11, 0) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
508 +#define QCA8K_EGREES_VLAN_PORT(_i, x) ((x) << QCA8K_EGREES_VLAN_PORT_SHIFT(_i))
509 #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
510
511 /* L3 registers */
512 --
513 cgit 1.2.3-1.el7
514
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