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1 From 4ba6e00c2f45bf4189ec6a8ef71b45346ae804f2 Mon Sep 17 00:00:00 2001
2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
3 Date: Thu, 28 Nov 2019 15:36:10 +0200
4 Subject: [PATCH] net: mscc: ocelot: do not force Felix MACs at lower speeds
5 than gigabit
6
7 In the LS1028A, the VSC9959 switch was integrated with an NXP PCS which
8 performs SGMII AN and rate adaptation autonomously. The MAC does not
9 need to know about this, and forcing the MAC speed to something else,
10 when connected to a 10/100 link partner, actually breaks the GMII
11 internal link between the MAC and the PCS.
12
13 Add a quirk system in the ocelot driver, and a first quirk called "PCS
14 performs rate adaptation", to distinguish the VSC7514 from the VSC9959
15 regarding this behavior.
16
17 Signed-off-by: Catalin Horghidan <catalin.horghidan@nxp.com>
18 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
19 ---
20 drivers/net/dsa/ocelot/felix.c | 1 +
21 drivers/net/dsa/ocelot/felix.h | 1 +
22 drivers/net/dsa/ocelot/felix_vsc9959.c | 1 +
23 drivers/net/ethernet/mscc/ocelot.c | 32 ++++++++++++++++++--------------
24 include/soc/mscc/ocelot.h | 7 +++++++
25 5 files changed, 28 insertions(+), 14 deletions(-)
26
27 --- a/drivers/net/dsa/ocelot/felix.c
28 +++ b/drivers/net/dsa/ocelot/felix.c
29 @@ -249,6 +249,7 @@ static int felix_init_structs(struct fel
30 ocelot->num_stats = felix->info->num_stats;
31 ocelot->shared_queue_sz = felix->info->shared_queue_sz;
32 ocelot->ops = felix->info->ops;
33 + ocelot->quirks = felix->info->quirks;
34
35 base = pci_resource_start(felix->pdev, felix->info->pci_bar);
36
37 --- a/drivers/net/dsa/ocelot/felix.h
38 +++ b/drivers/net/dsa/ocelot/felix.h
39 @@ -18,6 +18,7 @@ struct felix_info {
40 unsigned int num_stats;
41 int num_ports;
42 int pci_bar;
43 + unsigned long quirks;
44 };
45
46 extern struct felix_info felix_info_vsc9959;
47 --- a/drivers/net/dsa/ocelot/felix_vsc9959.c
48 +++ b/drivers/net/dsa/ocelot/felix_vsc9959.c
49 @@ -584,4 +584,5 @@ struct felix_info felix_info_vsc9959 = {
50 .shared_queue_sz = 128 * 1024,
51 .num_ports = 6,
52 .pci_bar = 4,
53 + .quirks = OCELOT_PCS_PERFORMS_RATE_ADAPTATION,
54 };
55 --- a/drivers/net/ethernet/mscc/ocelot.c
56 +++ b/drivers/net/ethernet/mscc/ocelot.c
57 @@ -409,27 +409,32 @@ static u16 ocelot_wm_enc(u16 value)
58 void ocelot_adjust_link(struct ocelot *ocelot, int port,
59 struct phy_device *phydev)
60 {
61 + int speed, mac_speed, mac_mode = DEV_MAC_MODE_CFG_FDX_ENA;
62 struct ocelot_port *ocelot_port = ocelot->ports[port];
63 - int speed, mode = 0;
64
65 - switch (phydev->speed) {
66 + if (ocelot->quirks & OCELOT_PCS_PERFORMS_RATE_ADAPTATION)
67 + speed = SPEED_1000;
68 + else
69 + speed = phydev->speed;
70 +
71 + switch (speed) {
72 case SPEED_10:
73 - speed = OCELOT_SPEED_10;
74 + mac_speed = OCELOT_SPEED_10;
75 break;
76 case SPEED_100:
77 - speed = OCELOT_SPEED_100;
78 + mac_speed = OCELOT_SPEED_100;
79 break;
80 case SPEED_1000:
81 - speed = OCELOT_SPEED_1000;
82 - mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
83 + mac_speed = OCELOT_SPEED_1000;
84 + mac_mode |= DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
85 break;
86 case SPEED_2500:
87 - speed = OCELOT_SPEED_2500;
88 - mode = DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
89 + mac_speed = OCELOT_SPEED_2500;
90 + mac_mode |= DEV_MAC_MODE_CFG_GIGA_MODE_ENA;
91 break;
92 default:
93 dev_err(ocelot->dev, "Unsupported PHY speed on port %d: %d\n",
94 - port, phydev->speed);
95 + port, speed);
96 return;
97 }
98
99 @@ -439,8 +444,7 @@ void ocelot_adjust_link(struct ocelot *o
100 return;
101
102 /* Only full duplex supported for now */
103 - ocelot_port_writel(ocelot_port, DEV_MAC_MODE_CFG_FDX_ENA |
104 - mode, DEV_MAC_MODE_CFG);
105 + ocelot_port_writel(ocelot_port, mac_mode, DEV_MAC_MODE_CFG);
106
107 if (ocelot->ops->pcs_init)
108 ocelot->ops->pcs_init(ocelot, port);
109 @@ -451,11 +455,11 @@ void ocelot_adjust_link(struct ocelot *o
110
111 /* Take MAC, Port, Phy (intern) and PCS (SGMII/Serdes) clock out of
112 * reset */
113 - ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(speed),
114 + ocelot_port_writel(ocelot_port, DEV_CLOCK_CFG_LINK_SPEED(mac_speed),
115 DEV_CLOCK_CFG);
116
117 /* No PFC */
118 - ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(speed),
119 + ocelot_write_gix(ocelot, ANA_PFC_PFC_CFG_FC_LINK_SPEED(mac_speed),
120 ANA_PFC_PFC_CFG, port);
121
122 /* Core: Enable port for frame transfer */
123 @@ -469,7 +473,7 @@ void ocelot_adjust_link(struct ocelot *o
124 SYS_MAC_FC_CFG_RX_FC_ENA | SYS_MAC_FC_CFG_TX_FC_ENA |
125 SYS_MAC_FC_CFG_ZERO_PAUSE_ENA |
126 SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
127 - SYS_MAC_FC_CFG_FC_LINK_SPEED(speed),
128 + SYS_MAC_FC_CFG_FC_LINK_SPEED(mac_speed),
129 SYS_MAC_FC_CFG, port);
130 ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
131 }
132 --- a/include/soc/mscc/ocelot.h
133 +++ b/include/soc/mscc/ocelot.h
134 @@ -404,6 +404,11 @@ enum ocelot_tag_prefix {
135 OCELOT_TAG_PREFIX_LONG,
136 };
137
138 +/* Hardware quirks (differences between switch instantiations) */
139 +enum {
140 + OCELOT_PCS_PERFORMS_RATE_ADAPTATION = BIT(0),
141 +};
142 +
143 struct ocelot;
144
145 struct ocelot_ops {
146 @@ -464,6 +469,8 @@ struct ocelot {
147 struct delayed_work stats_work;
148 struct workqueue_struct *stats_queue;
149
150 + unsigned long quirks;
151 +
152 u8 ptp:1;
153 struct ptp_clock *ptp_clock;
154 struct ptp_clock_info ptp_info;
Staging tree of Daniel Golle