git.openwrt.org Git - openwrt/staging/pepe2k.git/blob

   1 From dd58318c019f10bc94db36df66af6c55d4c0cbba Mon Sep 17 00:00:00 2001
   2 From: Abhishek Sahu <absahu@codeaurora.org>
   3 Date: Mon, 15 Jun 2020 23:05:59 +0200
   4 Subject: PCI: qcom: Change duplicate PCI reset to phy reset
   5
   6 The deinit issues reset_control_assert for PCI twice and does not contain
   7 phy reset.
   8
   9 Link: https://lore.kernel.org/r/20200615210608.21469-4-ansuelsmth@gmail.com
  10 Signed-off-by: Abhishek Sahu <absahu@codeaurora.org>
  11 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  12 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  13 Reviewed-by: Rob Herring <robh@kernel.org>
  14 Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  15 ---
  16  drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++----------
  17  1 file changed, 8 insertions(+), 10 deletions(-)
  18
  19 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  20 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  21 @@ -269,14 +269,14 @@ static void qcom_pcie_deinit_2_1_0(struc
  22  {
  23         struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
  24
  25 +       clk_disable_unprepare(res->phy_clk);
  26         reset_control_assert(res->pci_reset);
  27         reset_control_assert(res->axi_reset);
  28         reset_control_assert(res->ahb_reset);
  29         reset_control_assert(res->por_reset);
  30 -       reset_control_assert(res->pci_reset);
  31 +       reset_control_assert(res->phy_reset);
  32         clk_disable_unprepare(res->iface_clk);
  33         clk_disable_unprepare(res->core_clk);
  34 -       clk_disable_unprepare(res->phy_clk);
  35         clk_disable_unprepare(res->aux_clk);
  36         clk_disable_unprepare(res->ref_clk);
  37         regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies);
  38 @@ -314,12 +314,6 @@ static int qcom_pcie_init_2_1_0(struct q
  39                 goto err_clk_core;
  40         }
  41
  42 -       ret = clk_prepare_enable(res->phy_clk);
  43 -       if (ret) {
  44 -               dev_err(dev, "cannot prepare/enable phy clock\n");
  45 -               goto err_clk_phy;
  46 -       }
  47 -
  48         ret = clk_prepare_enable(res->aux_clk);
  49         if (ret) {
  50                 dev_err(dev, "cannot prepare/enable aux clock\n");
  51 @@ -372,6 +366,12 @@ static int qcom_pcie_init_2_1_0(struct q
  52                 return ret;
  53         }
  54
  55 +       ret = clk_prepare_enable(res->phy_clk);
  56 +       if (ret) {
  57 +               dev_err(dev, "cannot prepare/enable phy clock\n");
  58 +               goto err_deassert_ahb;
  59 +       }
  60 +
  61         /* wait for clock acquisition */
  62         usleep_range(1000, 1500);
  63
  64 @@ -389,8 +389,6 @@ err_deassert_ahb:
  65  err_clk_ref:
  66         clk_disable_unprepare(res->aux_clk);
  67  err_clk_aux:
  68 -       clk_disable_unprepare(res->phy_clk);
  69 -err_clk_phy:
  70         clk_disable_unprepare(res->core_clk);
  71  err_clk_core:
  72         clk_disable_unprepare(res->iface_clk);