a22d2726567fe1b590c01aab10ff0b5633a2d70c
[openwrt/staging/aparcar.git] /
1 From 2355a6546a053b1c16ebefd6ce1f0cccc00e1da5 Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
3 Date: Thu, 12 Oct 2017 10:21:25 +0200
4 Subject: [PATCH] net: phy: broadcom: support new device flag for setting
5 master mode
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 Some of Broadcom's PHYs run by default in slave mode with Automatic
11 Slave/Master configuration disabled. It stops them from working properly
12 with some devices.
13
14 So far it has been verified for BCM54210E and BCM50212E which don't
15 work well with Intel's I217-LM and I218-LM:
16 http://ark.intel.com/products/60019/Intel-Ethernet-Connection-I217-LM
17 http://ark.intel.com/products/71307/Intel-Ethernet-Connection-I218-LM
18 I was told there is massive ping loss.
19
20 This commit adds support for a new flag which can be set by an ethernet
21 driver to fixup PHY setup.
22
23 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
24 Signed-off-by: David S. Miller <davem@davemloft.net>
25 ---
26 drivers/net/phy/broadcom.c | 6 ++++++
27 include/linux/brcmphy.h | 1 +
28 2 files changed, 7 insertions(+)
29
30 --- a/drivers/net/phy/broadcom.c
31 +++ b/drivers/net/phy/broadcom.c
32 @@ -43,6 +43,12 @@ static int bcm54210e_config_init(struct
33 val &= ~BCM54810_SHD_CLK_CTL_GTXCLK_EN;
34 bcm_phy_write_shadow(phydev, BCM54810_SHD_CLK_CTL, val);
35
36 + if (phydev->dev_flags & PHY_BRCM_EN_MASTER_MODE) {
37 + val = phy_read(phydev, MII_CTRL1000);
38 + val |= CTL1000_AS_MASTER | CTL1000_ENABLE_MASTER;
39 + phy_write(phydev, MII_CTRL1000, val);
40 + }
41 +
42 return 0;
43 }
44
45 --- a/include/linux/brcmphy.h
46 +++ b/include/linux/brcmphy.h
47 @@ -64,6 +64,7 @@
48 #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000
49 #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000
50 #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000
51 +#define PHY_BRCM_EN_MASTER_MODE 0x00010000
52
53 /* Broadcom BCM7xxx specific workarounds */
54 #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff)