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1 From 21c29be6a69d3ef4f5a2e16272deb4845f8208ad Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <zajec5@gmail.com>
3 Date: Tue, 23 Aug 2016 07:37:43 +0200
4 Subject: [PATCH] ARM: BCM5301X: Add basic dts for BCM53573 based Tenda AC9
5 MIME-Version: 1.0
6 Content-Type: text/plain; charset=UTF-8
7 Content-Transfer-Encoding: 8bit
8
9 BCM53573 seems to be low priced alternative for Northstar chipsts. It
10 uses single core Cortex-A7 and doesn't have SDU or local (TWD) timer. It
11 was also stripped out of independent SPI controller and 2 GMACs.
12
13 DTS for Tenda AC9 isn't completed yet. It misses e.g. switch entry (we
14 still need some b53 fixes) and probably some clocks. It adds support for
15 basic features however and can be improved later.
16
17 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
18 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
19 ---
20 arch/arm/boot/dts/Makefile | 2 +
21 arch/arm/boot/dts/bcm47189-tenda-ac9.dts | 74 ++++++++++++++++
22 arch/arm/boot/dts/bcm53573.dtsi | 147 +++++++++++++++++++++++++++++++
23 3 files changed, 223 insertions(+)
24 create mode 100644 arch/arm/boot/dts/bcm47189-tenda-ac9.dts
25 create mode 100644 arch/arm/boot/dts/bcm53573.dtsi
26
27 --- a/arch/arm/boot/dts/Makefile
28 +++ b/arch/arm/boot/dts/Makefile
29 @@ -82,6 +82,8 @@ dtb-$(CONFIG_ARCH_BCM_5301X) += \
30 bcm94709.dtb \
31 bcm953012er.dtb \
32 bcm953012k.dtb
33 +dtb-$(CONFIG_ARCH_BCM_53573) += \
34 + bcm47189-tenda-ac9.dtb
35 dtb-$(CONFIG_ARCH_BCM_63XX) += \
36 bcm963138dvt.dtb
37 dtb-$(CONFIG_ARCH_BCM_CYGNUS) += \
38 --- /dev/null
39 +++ b/arch/arm/boot/dts/bcm47189-tenda-ac9.dts
40 @@ -0,0 +1,74 @@
41 +/*
42 + * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
43 + *
44 + * Licensed under the ISC license.
45 + */
46 +
47 +/dts-v1/;
48 +
49 +#include "bcm53573.dtsi"
50 +
51 +/ {
52 + compatible = "tenda,ac9", "brcm,bcm47189", "brcm,bcm53573";
53 + model = "Tenda AC9";
54 +
55 + chosen {
56 + bootargs = "console=ttyS0,115200 earlycon";
57 + };
58 +
59 + memory {
60 + reg = <0x00000000 0x08000000>;
61 + };
62 +
63 + leds {
64 + compatible = "gpio-leds";
65 +
66 + usb {
67 + label = "bcm53xx:blue:usb";
68 + gpios = <&chipcommon 1 GPIO_ACTIVE_HIGH>;
69 + linux,default-trigger = "default-off";
70 + };
71 +
72 + wps {
73 + label = "bcm53xx:blue:wps";
74 + gpios = <&chipcommon 10 GPIO_ACTIVE_HIGH>;
75 + linux,default-trigger = "default-off";
76 + };
77 +
78 + 5ghz {
79 + label = "bcm53xx:blue:5ghz";
80 + gpios = <&chipcommon 11 GPIO_ACTIVE_HIGH>;
81 + linux,default-trigger = "default-off";
82 + };
83 +
84 + system {
85 + label = "bcm53xx:blue:system";
86 + gpios = <&chipcommon 15 GPIO_ACTIVE_HIGH>;
87 + linux,default-trigger = "timer";
88 + };
89 + };
90 +
91 + gpio-keys {
92 + compatible = "gpio-keys";
93 + #address-cells = <1>;
94 + #size-cells = <0>;
95 +
96 + rfkill {
97 + label = "WiFi";
98 + linux,code = <KEY_RFKILL>;
99 + gpios = <&chipcommon 3 GPIO_ACTIVE_LOW>;
100 + };
101 +
102 + restart {
103 + label = "Reset";
104 + linux,code = <KEY_RESTART>;
105 + gpios = <&chipcommon 7 GPIO_ACTIVE_LOW>;
106 + };
107 +
108 + wps {
109 + label = "WPS";
110 + linux,code = <KEY_WPS_BUTTON>;
111 + gpios = <&chipcommon 9 GPIO_ACTIVE_LOW>;
112 + };
113 + };
114 +};
115 --- /dev/null
116 +++ b/arch/arm/boot/dts/bcm53573.dtsi
117 @@ -0,0 +1,147 @@
118 +/*
119 + * Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
120 + *
121 + * Licensed under the ISC license.
122 + */
123 +
124 +#include <dt-bindings/gpio/gpio.h>
125 +#include <dt-bindings/input/input.h>
126 +#include <dt-bindings/interrupt-controller/irq.h>
127 +#include <dt-bindings/interrupt-controller/arm-gic.h>
128 +#include "skeleton.dtsi"
129 +
130 +/ {
131 + interrupt-parent = <&gic>;
132 +
133 + chosen {
134 + stdout-path = &uart0;
135 + };
136 +
137 + cpus {
138 + #address-cells = <1>;
139 + #size-cells = <0>;
140 +
141 + cpu@0 {
142 + device_type = "cpu";
143 + compatible = "arm,cortex-a7";
144 + reg = <0x0>;
145 + };
146 + };
147 +
148 + mpcore {
149 + compatible = "simple-bus";
150 + ranges = <0x00000000 0x18310000 0x00008000>;
151 + #address-cells = <1>;
152 + #size-cells = <1>;
153 +
154 + gic: interrupt-controller@1000 {
155 + compatible = "arm,cortex-a7-gic";
156 + #interrupt-cells = <3>;
157 + #address-cells = <0>;
158 + interrupt-controller;
159 + reg = <0x1000 0x1000>,
160 + <0x2000 0x0100>;
161 + };
162 + };
163 +
164 + clocks {
165 + #address-cells = <1>;
166 + #size-cells = <1>;
167 + ranges;
168 +
169 + alp: oscillator {
170 + #clock-cells = <0>;
171 + compatible = "fixed-clock";
172 + clock-frequency = <40000000>;
173 + };
174 + };
175 +
176 + axi@18000000 {
177 + compatible = "brcm,bus-axi";
178 + reg = <0x18000000 0x1000>;
179 + ranges = <0x00000000 0x18000000 0x00100000>;
180 + #address-cells = <1>;
181 + #size-cells = <1>;
182 +
183 + #interrupt-cells = <1>;
184 + interrupt-map-mask = <0x000fffff 0xffff>;
185 + interrupt-map =
186 + /* ChipCommon */
187 + <0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
188 +
189 + /* IEEE 802.11 0 */
190 + <0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
191 +
192 + /* PCIe Controller 0 */
193 + <0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
194 + <0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
195 + <0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
196 + <0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
197 + <0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
198 + <0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
199 +
200 + /* USB 2.0 Controller */
201 + <0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
202 +
203 + /* Ethernet Controller 0 */
204 + <0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
205 +
206 + /* IEEE 802.11 1 */
207 + <0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
208 +
209 + /* Ethernet Controller 1 */
210 + <0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
211 +
212 + chipcommon: chipcommon@0 {
213 + compatible = "simple-bus";
214 + reg = <0x00000000 0x1000>;
215 + ranges;
216 +
217 + #address-cells = <1>;
218 + #size-cells = <1>;
219 +
220 + gpio-controller;
221 + #gpio-cells = <2>;
222 +
223 + uart0: serial@0300 {
224 + compatible = "ns16550a";
225 + reg = <0x0300 0x100>;
226 + interrupt-parent = <&gic>;
227 + interrupts = <GIC_PPI 16 IRQ_TYPE_LEVEL_HIGH>;
228 + clocks = <&alp>;
229 + status = "okay";
230 + };
231 + };
232 +
233 + usb2: usb2@4000 {
234 + reg = <0x4000 0x1000>;
235 + ranges;
236 + #address-cells = <1>;
237 + #size-cells = <1>;
238 +
239 + ehci: ehci@4000 {
240 + compatible = "generic-ehci";
241 + reg = <0x4000 0x1000>;
242 + interrupt-parent = <&gic>;
243 + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
244 + };
245 +
246 + ohci: ohci@d000 {
247 + #usb-cells = <0>;
248 +
249 + compatible = "generic-ohci";
250 + reg = <0xd000 0x1000>;
251 + interrupt-parent = <&gic>;
252 + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
253 + };
254 + };
255 +
256 + gmac0: ethernet@5000 {
257 + reg = <0x5000 0x1000>;
258 + };
259 +
260 + gmac1: ethernet@b000 {
261 + reg = <0xb000 0x1000>;
262 + };
263 + };
264 +};
Staging tree of Petr Stetiar