git.openwrt.org Git - openwrt/staging/stintel.git/blob

   1 From 0d4749abb6f7d042643ba1aa27a7388e8290b6f5 Mon Sep 17 00:00:00 2001
   2 From: Li Jun <jun.li@nxp.com>
   3 Date: Tue, 16 Apr 2019 14:02:38 +0800
   4 Subject: [PATCH] usb: dwc3: use suspend clock from dt to set power down scale
   5
   6 Since the new dwc3 use bulk clks including the suspend clk, so we can
   7 use it to calculate the power down scale value.
   8
   9 Acked-by: Peter Chen <peter.chen@nxp.com>
  10 Signed-off-by: Li Jun <jun.li@nxp.com>
  11 ---
  12  drivers/usb/dwc3/core.c | 21 +++++++++++++++++++++
  13  drivers/usb/dwc3/core.h |  1 +
  14  2 files changed, 22 insertions(+)
  15
  16 --- a/drivers/usb/dwc3/core.c
  17 +++ b/drivers/usb/dwc3/core.c
  18 @@ -894,6 +894,25 @@ static void dwc3_set_incr_burst_type(str
  19         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
  20  }
  21
  22 +static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
  23 +{
  24 +       u32 reg, scale;
  25 +
  26 +       if (dwc->num_clks == 0)
  27 +               return;
  28 +
  29 +       /*
  30 +        * The power down scale field specifies how many suspend_clk
  31 +        * periods fit into a 16KHz clock period. When performing
  32 +        * the division, round up the remainder.
  33 +        */
  34 +       scale = DIV_ROUND_UP(clk_get_rate(dwc->clks[2].clk), 16384);
  35 +       reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  36 +       reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
  37 +       reg |= DWC3_GCTL_PWRDNSCALE(scale);
  38 +       dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  39 +}
  40 +
  41  /**
  42   * dwc3_core_init - Low-level initialization of DWC3 Core
  43   * @dwc: Pointer to our controller context structure
  44 @@ -918,6 +937,8 @@ static int dwc3_core_init(struct dwc3 *d
  45                         dwc->maximum_speed = USB_SPEED_HIGH;
  46         }
  47
  48 +       dwc3_set_power_down_clk_scale(dwc);
  49 +
  50         ret = dwc3_phy_setup(dwc);
  51         if (ret)
  52                 goto err0;
  53 --- a/drivers/usb/dwc3/core.h
  54 +++ b/drivers/usb/dwc3/core.h
  55 @@ -223,6 +223,7 @@
  56
  57  /* Global Configuration Register */
  58  #define DWC3_GCTL_PWRDNSCALE(n)        ((n) << 19)
  59 +#define DWC3_GCTL_PWRDNSCALE_MASK      DWC3_GCTL_PWRDNSCALE(0x1fff)
  60  #define DWC3_GCTL_U2RSTECN     BIT(16)
  61  #define DWC3_GCTL_RAMCLKSEL(x) (((x) & DWC3_GCTL_CLK_MASK) << 6)
  62  #define DWC3_GCTL_CLK_BUS      (0)