git.openwrt.org Git - openwrt/staging/blocktrron.git/blob

   1 From f383b0770612838e78986231710c0a3afee4db42 Mon Sep 17 00:00:00 2001
   2 From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
   3 Date: Mon, 10 Jan 2022 12:49:27 +0100
   4 Subject: [PATCH 1/2] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Add dt binding header for resets lines in Mediatek MT7621 SoCs.
  10
  11 Acked-by: Rob Herring <robh@kernel.org>
  12 Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>
  13 Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  14 Link: https://lore.kernel.org/r/20220110114930.1406665-2-sergio.paracuellos@gmail.com
  15 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  16 ---
  17  include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++++++++++
  18  1 file changed, 37 insertions(+)
  19  create mode 100644 include/dt-bindings/reset/mt7621-reset.h
  20
  21 --- /dev/null
  22 +++ b/include/dt-bindings/reset/mt7621-reset.h
  23 @@ -0,0 +1,37 @@
  24 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  25 +/*
  26 + * Copyright (c) 2021 Sergio Paracuellos
  27 + * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
  28 + */
  29 +
  30 +#ifndef DT_BINDING_MT7621_RESET_H
  31 +#define DT_BINDING_MT7621_RESET_H
  32 +
  33 +#define MT7621_RST_SYS         0
  34 +#define MT7621_RST_MCM         2
  35 +#define MT7621_RST_HSDMA       5
  36 +#define MT7621_RST_FE          6
  37 +#define MT7621_RST_SPDIFTX     7
  38 +#define MT7621_RST_TIMER       8
  39 +#define MT7621_RST_INT         9
  40 +#define MT7621_RST_MC          10
  41 +#define MT7621_RST_PCM         11
  42 +#define MT7621_RST_PIO         13
  43 +#define MT7621_RST_GDMA                14
  44 +#define MT7621_RST_NFI         15
  45 +#define MT7621_RST_I2C         16
  46 +#define MT7621_RST_I2S         17
  47 +#define MT7621_RST_SPI         18
  48 +#define MT7621_RST_UART1       19
  49 +#define MT7621_RST_UART2       20
  50 +#define MT7621_RST_UART3       21
  51 +#define MT7621_RST_ETH         23
  52 +#define MT7621_RST_PCIE0       24
  53 +#define MT7621_RST_PCIE1       25
  54 +#define MT7621_RST_PCIE2       26
  55 +#define MT7621_RST_AUX_STCK    28
  56 +#define MT7621_RST_CRYPTO      29
  57 +#define MT7621_RST_SDXC                30
  58 +#define MT7621_RST_PPE         31
  59 +
  60 +#endif /* DT_BINDING_MT7621_RESET_H */