[openwrt/staging/ldir.git] /

From b752c8ed4ab83d47a585c363056d64fb978ef481 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Horia=20Geant=C4=83?= <horia.geanta@nxp.com>
Date: Fri, 27 Sep 2019 20:05:26 +0300
Subject: [PATCH] MLKU-114-2 crypto: caam - SCU firmware support
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Some i.MX8 processors, e.g. i.MX8QM (QM, QP), i.MX8QX (QXP, DX) have a
System Controller Firmware (SCFW) running on a dedicated Cortex-M core
that provides power, clock, and resource management.

caam driver needs to be aware of SCU f/w presence, since some things
are done differently:

1. clocks are under SCU f/w control and are turned on automatically

2. there is no access to controller's register page (note however that
some registers are aliased in job rings' register pages)

It's worth mentioning that due to this, MCFGR[PS] cannot be read
and driver assumes MCFGR[PS] = b'0 - engine using 32-bit address pointers.
This is in sync with the limitation imposed by the
SECO (Security Controller) ROM and f/w running on a dedicated Cortex-M.

3. as a consequence of "2.", part of the initialization is moved in
other f/w (SCU, TF-A etc.), e.g. RNG initialization

Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
---
 drivers/crypto/caam/ctrl.c   | 28 ++++++++++++++++++++++++++--
 drivers/crypto/caam/intern.h |  1 +
 2 files changed, 27 insertions(+), 2 deletions(-)

--- a/drivers/crypto/caam/ctrl.c
+++ b/drivers/crypto/caam/ctrl.c
@@ -596,6 +596,17 @@ static int caam_probe(struct platform_de
        caam_imx = (bool)imx_soc_match;
 
        if (imx_soc_match) {
+               np = of_find_compatible_node(NULL, NULL, "fsl,imx-scu");
+               ctrlpriv->scu_en = !!np;
+               of_node_put(np);
+
+               /*
+                * CAAM clocks cannot be controlled from kernel.
+                * They are automatically turned on by SCU f/w.
+                */
+               if (ctrlpriv->scu_en)
+                       goto iomap_ctrl;
+
                if (!imx_soc_match->data) {
                        dev_err(dev, "No clock data provided for i.MX SoC");
                        return -EINVAL;
@@ -606,7 +617,7 @@ static int caam_probe(struct platform_de
                        return ret;
        }
 
-
+iomap_ctrl:
        /* Get configuration properties from device tree */
        /* First, get register page */
        ctrl = devm_of_iomap(dev, nprop, 0, NULL);
@@ -646,7 +657,8 @@ static int caam_probe(struct platform_de
        caam_little_end = !(bool)(rd_reg32(&perfmon->status) &
                                  (CSTA_PLEND | CSTA_ALT_PLEND));
        comp_params = rd_reg32(&perfmon->comp_parms_ms);
-       if (comp_params & CTPR_MS_PS && rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
+       if (!ctrlpriv->scu_en && comp_params & CTPR_MS_PS &&
+           rd_reg32(&ctrl->mcr) & MCFGR_LONG_PTR)
                caam_ptr_sz = sizeof(u64);
        else
                caam_ptr_sz = sizeof(u32);
@@ -696,6 +708,9 @@ static int caam_probe(struct platform_de
        /* Get the IRQ of the controller (for security violations only) */
        ctrlpriv->secvio_irq = irq_of_parse_and_map(nprop, 0);
 
+       if (ctrlpriv->scu_en)
+               goto set_dma_mask;
+
        /*
         * Enable DECO watchdogs and, if this is a PHYS_ADDR_T_64BIT kernel,
         * long pointers in master configuration register.
@@ -739,6 +754,7 @@ static int caam_probe(struct platform_de
                              JRSTART_JR1_START | JRSTART_JR2_START |
                              JRSTART_JR3_START);
 
+set_dma_mask:
        ret = dma_set_mask_and_coherent(dev, caam_get_dma_mask(dev));
        if (ret) {
                dev_err(dev, "dma_set_mask_and_coherent failed (%d)\n", ret);
@@ -785,6 +801,9 @@ static int caam_probe(struct platform_de
                return -ENOMEM;
        }
 
+       if (ctrlpriv->scu_en)
+               goto report_live;
+
        if (ctrlpriv->era < 10) {
                rng_vid = (rd_reg32(&perfmon->cha_id_ls) &
                           CHA_ID_LS_RNG_MASK) >> CHA_ID_LS_RNG_SHIFT;
@@ -865,6 +884,7 @@ static int caam_probe(struct platform_de
 
        /* NOTE: RTIC detection ought to go here, around Si time */
 
+report_live:
        caam_id = (u64)rd_reg32(&perfmon->caam_id_ms) << 32 |
                  (u64)rd_reg32(&perfmon->caam_id_ls);
 
@@ -908,6 +928,9 @@ static int caam_probe(struct platform_de
                            ctrlpriv->ctl, &perfmon->status,
                            &caam_fops_u32_ro);
 
+       if (ctrlpriv->scu_en)
+               goto probe_jrs;
+
        /* Internal covering keys (useful in non-secure mode only) */
        ctrlpriv->ctl_kek_wrap.data = (__force void *)&ctrlpriv->ctrl->kek[0];
        ctrlpriv->ctl_kek_wrap.size = KEK_KEY_SIZE * sizeof(u32);
@@ -925,6 +948,7 @@ static int caam_probe(struct platform_de
                            &ctrlpriv->ctl_tdsk_wrap);
 #endif
 
+probe_jrs:
        ret = devm_of_platform_populate(dev);
        if (ret)
                dev_err(dev, "JR platform devices creation error\n");
--- a/drivers/crypto/caam/intern.h
+++ b/drivers/crypto/caam/intern.h
@@ -82,6 +82,7 @@ struct caam_drv_private {
        u8 total_jobrs;         /* Total Job Rings in device */
        u8 qi_present;          /* Nonzero if QI present in device */
        u8 mc_en;               /* Nonzero if MC f/w is active */
+       u8 scu_en;              /* Nonzero if SCU f/w is active */
        int secvio_irq;         /* Security violation interrupt number */
        int virt_en;            /* Virtualization enabled in CAAM */
        int era;                /* CAAM Era (internal HW revision) */