1 From 1ffe76d5ae78553948d67a978acd9945c2f0a175 Mon Sep 17 00:00:00 2001
2 From: Shiji Yang <yangshiji66@outlook.com>
3 Date: Thu, 19 Oct 2023 19:58:56 +0800
4 Subject: wifi: rt2x00: improve MT7620 register initialization
6 1. Do not hard reset the BBP. We can use soft reset instead. This
7 change has some help to the calibration failure issue.
8 2. Enable falling back to legacy rate from the HT/RTS rate by
9 setting the HT_FBK_TO_LEGACY register.
10 3. Implement MCS rate specific maximum PSDU size. It can improve
11 the transmission quality under the low RSSI condition.
12 4. Set BBP_84 register value to 0x19. This is used for extension
13 channel overlapping IOT.
15 Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
16 Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
17 Signed-off-by: Kalle Valo <kvalo@kernel.org>
18 Link: https://lore.kernel.org/r/TYAP286MB031553CCD4B7A3B89C85935DBCD4A@TYAP286MB0315.JPNP286.PROD.OUTLOOK.COM
20 drivers/net/wireless/ralink/rt2x00/rt2800.h | 18 ++++++++++++++++++
21 drivers/net/wireless/ralink/rt2x00/rt2800lib.c | 24 ++++++++++++++++++++++++
22 drivers/net/wireless/ralink/rt2x00/rt2800mmio.c | 3 +++
23 3 files changed, 45 insertions(+)
25 --- a/drivers/net/wireless/ralink/rt2x00/rt2800.h
26 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800.h
28 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
31 + * AMPDU_MAX_LEN_20M1S: Per MCS max A-MPDU length, 20 MHz, MCS 0-7
32 + * AMPDU_MAX_LEN_20M2S: Per MCS max A-MPDU length, 20 MHz, MCS 8-15
33 + * AMPDU_MAX_LEN_40M1S: Per MCS max A-MPDU length, 40 MHz, MCS 0-7
34 + * AMPDU_MAX_LEN_40M2S: Per MCS max A-MPDU length, 40 MHz, MCS 8-15
35 + * Maximum A-MPDU length = 2^(AMPDU_MAX - 5) kilobytes
37 +#define AMPDU_MAX_LEN_20M1S 0x1030
38 +#define AMPDU_MAX_LEN_20M2S 0x1034
39 +#define AMPDU_MAX_LEN_40M1S 0x1038
40 +#define AMPDU_MAX_LEN_40M2S 0x103C
43 * AMPDU_BA_WINSIZE: Force BlockAck window size
44 * FORCE_WINSIZE_ENABLE:
45 * 0: Disable forcing of BlockAck window size
46 @@ -1545,6 +1557,12 @@
48 #define EXP_ACK_TIME 0x1380
51 + * HT_FBK_TO_LEGACY: Enable/Disable HT/RTS fallback to OFDM/CCK rate
52 + * Not available for legacy SoCs
54 +#define HT_FBK_TO_LEGACY 0x1384
57 #define TX_PWR_CFG_5 0x1384
58 #define TX_PWR_CFG_5_MCS16_CH0 FIELD32(0x0000000f)
59 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
60 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
61 @@ -5851,6 +5851,7 @@ static int rt2800_init_registers(struct
62 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
69 @@ -5860,6 +5861,19 @@ static int rt2800_init_registers(struct
73 + if (rt2x00_rt(rt2x00dev, RT6352)) {
74 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x01);
76 + bbp = rt2800_bbp_read(rt2x00dev, 21);
78 + rt2800_bbp_write(rt2x00dev, 21, bbp);
79 + bbp = rt2800_bbp_read(rt2x00dev, 21);
81 + rt2800_bbp_write(rt2x00dev, 21, bbp);
83 + rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00);
86 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
87 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
89 @@ -6013,6 +6027,14 @@ static int rt2800_init_registers(struct
90 reg = rt2800_register_read(rt2x00dev, TX_ALC_CFG_1);
91 rt2x00_set_field32(®, TX_ALC_CFG_1_ROS_BUSY_EN, 0);
92 rt2800_register_write(rt2x00dev, TX_ALC_CFG_1, reg);
94 + rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M1S, 0x77754433);
95 + rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_20M2S, 0x77765543);
96 + rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M1S, 0x77765544);
97 + rt2800_register_write(rt2x00dev, AMPDU_MAX_LEN_40M2S, 0x77765544);
99 + rt2800_register_write(rt2x00dev, HT_FBK_TO_LEGACY, 0x1010);
102 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
103 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
104 @@ -7231,6 +7253,8 @@ static void rt2800_init_bbp_6352(struct
105 rt2800_bbp_dcoc_write(rt2x00dev, 159, 0x64);
107 rt2800_bbp4_mac_if_ctrl(rt2x00dev);
109 + rt2800_bbp_write(rt2x00dev, 84, 0x19);
112 static void rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
113 --- a/drivers/net/wireless/ralink/rt2x00/rt2800mmio.c
114 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800mmio.c
115 @@ -760,6 +760,9 @@ int rt2800mmio_init_registers(struct rt2
117 rt2x00mmio_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
119 + if (rt2x00_rt(rt2x00dev, RT6352))
123 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
124 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);