git.openwrt.org Git - openwrt/staging/luka.git/blob

   1 From patchwork Fri Jul 13 11:32:42 2018
   2 Content-Type: text/plain; charset="utf-8"
   3 MIME-Version: 1.0
   4 Content-Transfer-Encoding: 7bit
   5 Subject: serial8250 on tegra hsuart: recover from spurious interrupts due to
   6  tegra2 silicon bug
   7 X-Patchwork-Submitter: "David R. Piegdon" <lkml@p23q.org>
   8 X-Patchwork-Id: 943440
   9 Message-Id: <4676ea34-69ce-5422-1ded-94218b89f7d9@p23q.org>
  10 To: linux-tegra@vger.kernel.org
  11 Date: Fri, 13 Jul 2018 11:32:42 +0000
  12 From: "David R. Piegdon" <lkml@p23q.org>
  13 List-Id: <linux-tegra.vger.kernel.org>
  14
  15 Hi,
  16 a while back I sent a few mails regarding spurious interrupts in the
  17 UARTA (hsuart) block of the Tegra2 SoC, when using the 8250 driver for
  18 it instead of the hsuart driver. After going down a pretty deep
  19 debugging/testing hole, I think I found a patch that fixes the issue. So
  20 far testing in a reboot-cycle suggests that the error frequency dropped
  21 from >3% of all reboots to at least <0.05% of all reboots. Tests
  22 continue to run over the weekend.
  23
  24 The patch below already is a second iteration; the first did not reset
  25 the MCR or contain the lines below '// clear interrupts'. This resulted
  26 in no more spurious interrupts, but in a few % of spurious interrupts
  27 that were recovered the UART block did not receive any characters any
  28 more. So further resetting was required to fully reacquire operational
  29 state of the UART block.
  30
  31 I'd love any comments/suggestions on this!
  32
  33 Cheers,
  34
  35 David
  36
  37 --- a/drivers/tty/serial/8250/8250_core.c
  38 +++ b/drivers/tty/serial/8250/8250_core.c
  39 @@ -136,6 +136,38 @@ static irqreturn_t serial8250_interrupt(
  40                                 "serial8250: too much work for irq%d\n", irq);
  41                         break;
  42                 }
  43 +
  44 +#ifdef CONFIG_ARCH_TEGRA_2x_SOC
  45 +               if (!handled && (port->type == PORT_TEGRA)) {
  46 +                       /*
  47 +                        * Fix Tegra 2 CPU silicon bug where sometimes
  48 +                        * "TX holding register empty" interrupts result in a
  49 +                        * bad (metastable?) state in Tegras HSUART IP core.
  50 +                        * Only way to recover seems to be to reset all
  51 +                        * interrupts as well as the TX queue and the MCR.
  52 +                        * But we don't want to loose any outgoing characters,
  53 +                        * so only do it if the RX and TX queues are empty.
  54 +                        */
  55 +                       unsigned char lsr = port->serial_in(port, UART_LSR);
  56 +                       const unsigned char fifo_empty_mask =
  57 +                                               (UART_LSR_TEMT | UART_LSR_THRE);
  58 +                       if (((lsr & (UART_LSR_DR | fifo_empty_mask)) ==
  59 +                                                       fifo_empty_mask)) {
  60 +                               port->serial_out(port, UART_IER, 0);
  61 +                               port->serial_out(port, UART_MCR, 0);
  62 +                               serial8250_clear_and_reinit_fifos(up);
  63 +                               port->serial_out(port, UART_MCR, up->mcr);
  64 +                               port->serial_out(port, UART_IER, up->ier);
  65 +                               // clear interrupts
  66 +                               serial_port_in(port, UART_LSR);
  67 +                               serial_port_in(port, UART_RX);
  68 +                               serial_port_in(port, UART_IIR);
  69 +                               serial_port_in(port, UART_MSR);
  70 +                               up->lsr_saved_flags = 0;
  71 +                               up->msr_saved_flags = 0;
  72 +                       }
  73 +               }
  74 +#endif
  75         } while (l != end);
  76
  77         spin_unlock(&i->lock);