git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 49502408007b77ff290ce62e6218cefaeedcb31a Mon Sep 17 00:00:00 2001
   2 From: Vasily Khoruzhick <anarsoul@gmail.com>
   3 Date: Thu, 9 Mar 2023 17:03:49 -0800
   4 Subject: [PATCH] mmc: sdhci-of-dwcmshc: properly determine max clock on
   5  Rockchip
   6
   7 Currently .get_max_clock returns the current clock rate for cclk_emmc
   8 on rk35xx, thus max clock gets set to whatever bootloader set it to.
   9
  10 In case of u-boot, it is intentionally reset to 50 MHz if it boots
  11 from eMMC, see mmc_deinit() in u-boot sources. As a result, HS200 and
  12 HS400 modes are never selected by Linux, because dwcmshc_rk35xx_postinit
  13 clears appropriate caps if host->mmc->f_max is < 52MHz
  14
  15 cclk_emmc is not a fixed clock on rk35xx, so using
  16 sdhci_pltfm_clk_get_max_clock is not appropriate here.
  17
  18 Implement rk35xx_get_max_clock that returns actual max clock for cclk_emmc.
  19
  20 Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
  21 Acked-by: Adrian Hunter <adrian.hunter@intel.com>
  22 Link: https://lore.kernel.org/r/20230310010349.509132-1-anarsoul@gmail.com
  23 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
  24 ---
  25  drivers/mmc/host/sdhci-of-dwcmshc.c | 9 ++++++++-
  26  1 file changed, 8 insertions(+), 1 deletion(-)
  27
  28 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c
  29 +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
  30 @@ -126,6 +126,13 @@ static unsigned int dwcmshc_get_max_cloc
  31                 return pltfm_host->clock;
  32  }
  33
  34 +static unsigned int rk35xx_get_max_clock(struct sdhci_host *host)
  35 +{
  36 +       struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
  37 +
  38 +       return clk_round_rate(pltfm_host->clk, ULONG_MAX);
  39 +}
  40 +
  41  static void dwcmshc_check_auto_cmd23(struct mmc_host *mmc,
  42                                      struct mmc_request *mrq)
  43  {
  44 @@ -343,7 +350,7 @@ static const struct sdhci_ops sdhci_dwcm
  45         .set_clock              = dwcmshc_rk3568_set_clock,
  46         .set_bus_width          = sdhci_set_bus_width,
  47         .set_uhs_signaling      = dwcmshc_set_uhs_signaling,
  48 -       .get_max_clock          = sdhci_pltfm_clk_get_max_clock,
  49 +       .get_max_clock          = rk35xx_get_max_clock,
  50         .reset                  = rk35xx_sdhci_reset,
  51         .adma_write_desc        = dwcmshc_adma_write_desc,
  52  };