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1 From 8fd1ab38e922383fa87db60c48c44ab0d5e6f1c1 Mon Sep 17 00:00:00 2001
2 From: Li Yang <leoyang.li@nxp.com>
3 Date: Thu, 2 May 2019 15:52:49 -0500
4 Subject: [PATCH] arm64: dts: ls1012a: accumulated change for ls1012a boards
5
6 commit 65c558ec270003e8e99cb58c940d3b913d08fa39
7 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
8 Date: Tue May 15 08:47:19 2018 +0800
9
10 arm64: dts: ls1012a: correct the register range of dcfg
11
12 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
13
14 commit 8f7b4cded4ea1fca53516ae8f5d5bc89af291f26
15 Author: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
16 Date: Mon May 7 11:52:04 2018 +0530
17
18 arm64: dts: ls1012a: Add LS1012A-FRWY board support
19
20 LS1012A-FRWY is a different design from LS1012A-FRDM,
21 but has some common SoC features. Key feature on this
22 board is 2x1G SGMII PFE MAC, Micro SD, USB 3.0, DDR,
23 QuadSPI, Audio, UART.
24
25 Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
26
27 commit 94fc77837b3b6f4213a49b29ddc3e09e38ae5fbb
28 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
29 Date: Mon Apr 2 16:16:47 2018 +0800
30
31 arm64: dts: ls1012a: add dts entry for A-010650
32
33 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
34
35 commit d4164a6d8cffd8f09c451073754834d58b7ace19
36 Author: Suresh Gupta <suresh.gupta@nxp.com>
37 Date: Thu Feb 1 23:44:15 2018 +0530
38
39 arm64: dts: freescale: ls1012a: Add DT nodes for qspi
40
41 Signed-off-by: Abhimanyu Saini <abhimanyu.saini@nxp.com>
42 Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com>
43
44 commit 4fdc98a03492b732a48426a4180f7d6a36847e71
45 Author: Zhang Ying-22455 <ying.zhang22455@nxp.com>
46 Date: Wed Nov 1 10:31:47 2017 +0800
47
48 arm64: dts: ls1012a: correct the i2c clock to 1/4 platform pll
49
50 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
51
52 commit bb534725996b92aff853a4dee43738629fd4ac08
53 Author: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
54 Date: Wed Nov 29 06:31:23 2017 +0530
55
56 arm64: dts: freescale: ls1012a: Disable PCIe node as default
57
58 Keep PCIe node in "disabled" status as SoC default.
59 Only enable it for boards with PCIe circuit designed,
60 such as LS1012ARDB and LS1012AQDS.
61
62 Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com>
63
64 commit 6b9a3244baba2c5126f349800ecaad83ba97ee47
65 Author: Calvin Johnson <calvin.johnson@nxp.com>
66 Date: Mon Oct 16 12:25:19 2017 +0530
67
68 arm64: dts: freescale: ls1012a: fix RGMII tx delay issue
69
70 Recently logic to enable RGMII tx delay was changed by
71 below patch.
72
73 https://patchwork.kernel.org/patch/9447581/
74
75 Based on the patch, enabling tx delay again using rgmii-txid.
76
77 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
78 Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
79
80 commit 1e17e247088f6e2c08041559e38053b70a9d2bbe
81 Author: Calvin Johnson <calvin.johnson@nxp.com>
82 Date: Sat Sep 16 14:20:23 2017 +0530
83
84 arm64: dts: freescale: ls1012a: update with pppfe support
85
86 Update ls1012a dtsi and platform dts files with
87 support for ppfe.
88
89 Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com>
90 Signed-off-by: Anjaneyulu Jagarlmudi <anji.jagarlmudi@nxp.com>
91
92 commit e9661ed864d2a9d437057f97729410bb9af994f2
93 Author: Suresh Gupta <suresh.gupta@nxp.com>
94 Date: Tue May 16 17:17:21 2017 +0530
95
96 arm64: dts: ls1012a: add the DTS node for QSPI support
97
98 There is a s25fs512s qspi flash on QDS, RDB and FRDM board.
99
100 Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
101
102 commit ed9c51239461fe0322da2e93f50033ea0d05bc4f
103 Author: Chenhui Zhao <chenhui.zhao@nxp.com>
104 Date: Fri May 5 17:45:15 2017 +0800
105
106 arm64: dts: ls1012a: add ftm0 node
107
108 Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
109 ---
110 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts | 58 ++++++++++++++++++
111 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts | 62 ++++++++++++++++++++
112 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts | 62 ++++++++++++++++++++
113 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 68 +++++++++++++++++++++-
114 4 files changed, 248 insertions(+), 2 deletions(-)
115
116 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
117 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts
118 @@ -13,6 +13,11 @@
119 model = "LS1012A Freedom Board";
120 compatible = "fsl,ls1012a-frdm", "fsl,ls1012a";
121
122 + aliases {
123 + ethernet0 = &pfe_mac0;
124 + ethernet1 = &pfe_mac1;
125 + };
126 +
127 sys_mclk: clock-mclk {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 @@ -74,6 +79,44 @@
131 };
132 };
133
134 +&pfe {
135 + status = "okay";
136 + #address-cells = <1>;
137 + #size-cells = <0>;
138 +
139 + ethernet@0 {
140 + compatible = "fsl,pfe-gemac-port";
141 + #address-cells = <1>;
142 + #size-cells = <0>;
143 + reg = <0x0>; /* GEM_ID */
144 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
145 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
146 + fsl,mdio-mux-val = <0x0>;
147 + phy-mode = "sgmii";
148 + fsl,pfe-phy-if-flags = <0x0>;
149 +
150 + mdio@0 {
151 + reg = <0x1>; /* enabled/disabled */
152 + };
153 + };
154 +
155 + ethernet@1 {
156 + compatible = "fsl,pfe-gemac-port";
157 + #address-cells = <1>;
158 + #size-cells = <0>;
159 + reg = <0x1>; /* GEM_ID */
160 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
161 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
162 + fsl,mdio-mux-val = <0x0>;
163 + phy-mode = "sgmii";
164 + fsl,pfe-phy-if-flags = <0x0>;
165 +
166 + mdio@0 {
167 + reg = <0x0>; /* enabled/disabled */
168 + };
169 + };
170 +};
171 +
172 &sai2 {
173 status = "okay";
174 };
175 @@ -81,3 +124,18 @@
176 &sata {
177 status = "okay";
178 };
179 +
180 +&qspi {
181 + status = "okay";
182 + qflash0: s25fs512s@0 {
183 + compatible = "spansion,m25p80";
184 + #address-cells = <1>;
185 + #size-cells = <1>;
186 + spi-max-frequency = <20000000>;
187 + m25p,fast-read;
188 + reg = <0>;
189 + spi-rx-bus-width = <2>;
190 + spi-tx-bus-width = <2>;
191 + };
192 +
193 +};
194 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
195 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts
196 @@ -13,6 +13,11 @@
197 model = "LS1012A QDS Board";
198 compatible = "fsl,ls1012a-qds", "fsl,ls1012a";
199
200 + aliases {
201 + ethernet0 = &pfe_mac0;
202 + ethernet1 = &pfe_mac1;
203 + };
204 +
205 sys_mclk: clock-mclk {
206 compatible = "fixed-clock";
207 #clock-cells = <0>;
208 @@ -57,6 +62,10 @@
209 };
210 };
211
212 +&pcie {
213 + status = "okay";
214 +};
215 +
216 &dspi {
217 bus-num = <0>;
218 status = "okay";
219 @@ -128,6 +137,44 @@
220 };
221 };
222
223 +&pfe {
224 + status = "okay";
225 + #address-cells = <1>;
226 + #size-cells = <0>;
227 +
228 + ethernet@0 {
229 + compatible = "fsl,pfe-gemac-port";
230 + #address-cells = <1>;
231 + #size-cells = <0>;
232 + reg = <0x0>; /* GEM_ID */
233 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
234 + fsl,gemac-phy-id = <0x1>; /* PHY_ID */
235 + fsl,mdio-mux-val = <0x2>;
236 + phy-mode = "sgmii-2500";
237 + fsl,pfe-phy-if-flags = <0x0>;
238 +
239 + mdio@0 {
240 + reg = <0x1>; /* enabled/disabled */
241 + };
242 + };
243 +
244 + ethernet@1 {
245 + compatible = "fsl,pfe-gemac-port";
246 + #address-cells = <1>;
247 + #size-cells = <0>;
248 + reg = <0x1>; /* GEM_ID */
249 + fsl,gemac-bus-id = <0x1>; /* BUS_ID */
250 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
251 + fsl,mdio-mux-val = <0x3>;
252 + phy-mode = "sgmii-2500";
253 + fsl,pfe-phy-if-flags = <0x0>;
254 +
255 + mdio@0 {
256 + reg = <0x0>; /* enabled/disabled */
257 + };
258 + };
259 +};
260 +
261 &sai2 {
262 status = "okay";
263 };
264 @@ -135,3 +182,18 @@
265 &sata {
266 status = "okay";
267 };
268 +
269 +&qspi {
270 + status = "okay";
271 + qflash0: s25fs512s@0 {
272 + compatible = "spansion,m25p80";
273 + #address-cells = <1>;
274 + #size-cells = <1>;
275 + spi-max-frequency = <20000000>;
276 + m25p,fast-read;
277 + reg = <0>;
278 + spi-rx-bus-width = <2>;
279 + spi-tx-bus-width = <2>;
280 + };
281 +
282 +};
283 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
284 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts
285 @@ -12,6 +12,15 @@
286 / {
287 model = "LS1012A RDB Board";
288 compatible = "fsl,ls1012a-rdb", "fsl,ls1012a";
289 +
290 + aliases {
291 + ethernet0 = &pfe_mac0;
292 + ethernet1 = &pfe_mac1;
293 + };
294 +};
295 +
296 +&pcie {
297 + status = "okay";
298 };
299
300 &duart0 {
301 @@ -38,3 +47,56 @@
302 &sata {
303 status = "okay";
304 };
305 +
306 +&pfe {
307 + status = "okay";
308 + #address-cells = <1>;
309 + #size-cells = <0>;
310 +
311 + ethernet@0 {
312 + compatible = "fsl,pfe-gemac-port";
313 + #address-cells = <1>;
314 + #size-cells = <0>;
315 + reg = <0x0>; /* GEM_ID */
316 + fsl,gemac-bus-id = <0x0>; /* BUS_ID */
317 + fsl,gemac-phy-id = <0x2>; /* PHY_ID */
318 + fsl,mdio-mux-val = <0x0>;
319 + phy-mode = "sgmii";
320 + fsl,pfe-phy-if-flags = <0x0>;
321 +
322 + mdio@0 {
323 + reg = <0x1>; /* enabled/disabled */
324 + };
325 + };
326 +
327 + ethernet@1 {
328 + compatible = "fsl,pfe-gemac-port";
329 + #address-cells = <1>;
330 + #size-cells = <0>;
331 + reg = <0x1>; /* GEM_ID */
332 + fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */
333 + fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */
334 + fsl,mdio-mux-val = <0x0>;
335 + phy-mode = "rgmii-txid";
336 + fsl,pfe-phy-if-flags = <0x0>;
337 +
338 + mdio@0 {
339 + reg = <0x0>; /* enabled/disabled */
340 + };
341 + };
342 +};
343 +
344 +&qspi {
345 + status = "okay";
346 + qflash0: s25fs512s@0 {
347 + compatible = "spansion,m25p80";
348 + #address-cells = <1>;
349 + #size-cells = <1>;
350 + spi-max-frequency = <20000000>;
351 + m25p,fast-read;
352 + reg = <0>;
353 + spi-rx-bus-width = <2>;
354 + spi-tx-bus-width = <2>;
355 + };
356 +
357 +};
358 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
359 +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
360 @@ -260,7 +260,7 @@
361 dcfg: dcfg@1ee0000 {
362 compatible = "fsl,ls1012a-dcfg",
363 "syscon";
364 - reg = <0x0 0x1ee0000 0x0 0x10000>;
365 + reg = <0x0 0x1ee0000 0x0 0x1000>;
366 big-endian;
367 };
368
369 @@ -317,13 +317,23 @@
370 #thermal-sensor-cells = <1>;
371 };
372
373 + ftm0: ftm0@29d0000 {
374 + compatible = "fsl,ftm-alarm";
375 + reg = <0x0 0x29d0000 0x0 0x10000>,
376 + <0x0 0x1ee2140 0x0 0x4>;
377 + reg-names = "ftm", "FlexTimer1";
378 + interrupts = <0 86 0x4>;
379 + big-endian;
380 + };
381 +
382 i2c0: i2c@2180000 {
383 - compatible = "fsl,vf610-i2c";
384 + compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c";
385 #address-cells = <1>;
386 #size-cells = <0>;
387 reg = <0x0 0x2180000 0x0 0x10000>;
388 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>;
389 clocks = <&clockgen 4 3>;
390 + scl-gpios = <&gpio0 13 0>;
391 status = "disabled";
392 };
393
394 @@ -395,6 +405,20 @@
395 big-endian;
396 };
397
398 + qspi: spi@1550000 {
399 + compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi";
400 + #address-cells = <1>;
401 + #size-cells = <0>;
402 + reg = <0x0 0x1550000 0x0 0x10000>,
403 + <0x0 0x40000000 0x0 0x10000000>;
404 + reg-names = "QuadSPI", "QuadSPI-memory";
405 + interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
406 + clock-names = "qspi_en", "qspi";
407 + clocks = <&clockgen 4 0>, <&clockgen 4 0>;
408 + big-endian;
409 + status = "disabled";
410 + };
411 +
412 sai1: sai@2b50000 {
413 #sound-dai-cells = <0>;
414 compatible = "fsl,vf610-sai";
415 @@ -499,6 +523,46 @@
416 <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>;
417 status = "disabled";
418 };
419 +
420 + rcpm: rcpm@1ee2000 {
421 + compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1";
422 + reg = <0x0 0x1ee2000 0x0 0x1000>;
423 + fsl,#rcpm-wakeup-cells = <1>;
424 + };
425 + };
426 +
427 + reserved-memory {
428 + #address-cells = <2>;
429 + #size-cells = <2>;
430 + ranges;
431 +
432 + pfe_reserved: packetbuffer@83400000 {
433 + reg = <0 0x83400000 0 0xc00000>;
434 + };
435 + };
436 +
437 + pfe: pfe@04000000 {
438 + compatible = "fsl,pfe";
439 + reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */
440 + <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */
441 + reg-names = "pfe", "pfe-ddr";
442 + fsl,pfe-num-interfaces = <0x2>;
443 + interrupts = <0 172 0x4>, /* HIF interrupt */
444 + <0 173 0x4>, /*HIF_NOCPY interrupt */
445 + <0 174 0x4>; /* WoL interrupt */
446 + interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol";
447 + memory-region = <&pfe_reserved>;
448 + fsl,pfe-scfg = <&scfg 0>;
449 + fsl,rcpm-wakeup = <&rcpm 0xf0000020>;
450 + clocks = <&clockgen 4 0>;
451 + clock-names = "pfe";
452 +
453 + status = "okay";
454 + pfe_mac0: ethernet@0 {
455 + };
456 +
457 + pfe_mac1: ethernet@1 {
458 + };
459 };
460
461 firmware {
Staging tree of Jo-Philipp Wich