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1 From e1aa2a770cc5f4d46693bb491ed2ca7f066c3585 Mon Sep 17 00:00:00 2001
2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
3 Date: Mon, 6 Jan 2020 14:30:41 +0200
4 Subject: [PATCH] Revert "net: mscc: ocelot: introduce more focused PCS ops for
5 PHYLINK"
6
7 This reverts commit 423c8b04007c85907f8f514de459ebc8541f0a54.
8
9 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
10 ---
11 drivers/net/ethernet/mscc/ocelot.c | 36 ++++++++++++++++++++++++--------
12 drivers/net/ethernet/mscc/ocelot_board.c | 35 +------------------------------
13 include/soc/mscc/ocelot.h | 12 +++--------
14 3 files changed, 31 insertions(+), 52 deletions(-)
15
16 --- a/drivers/net/ethernet/mscc/ocelot.c
17 +++ b/drivers/net/ethernet/mscc/ocelot.c
18 @@ -410,25 +410,43 @@ void ocelot_phylink_validate(struct ocel
19 unsigned long *supported,
20 struct phylink_link_state *state)
21 {
22 - if (ocelot->ops->pcs_validate)
23 - ocelot->ops->pcs_validate(ocelot, port, supported, state);
24 + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
25 +
26 + if (state->interface != PHY_INTERFACE_MODE_NA &&
27 + state->interface != PHY_INTERFACE_MODE_GMII &&
28 + state->interface != PHY_INTERFACE_MODE_SGMII &&
29 + state->interface != PHY_INTERFACE_MODE_QSGMII) {
30 + bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
31 + return;
32 + }
33 +
34 + /* No half-duplex. */
35 + phylink_set_port_modes(mask);
36 + phylink_set(mask, Autoneg);
37 + phylink_set(mask, Pause);
38 + phylink_set(mask, Asym_Pause);
39 + phylink_set(mask, 10baseT_Full);
40 + phylink_set(mask, 100baseT_Full);
41 + phylink_set(mask, 1000baseT_Full);
42 + phylink_set(mask, 2500baseT_Full);
43 +
44 + bitmap_and(supported, supported, mask,
45 + __ETHTOOL_LINK_MODE_MASK_NBITS);
46 + bitmap_and(state->advertising, state->advertising, mask,
47 + __ETHTOOL_LINK_MODE_MASK_NBITS);
48 }
49 EXPORT_SYMBOL(ocelot_phylink_validate);
50
51 void ocelot_phylink_mac_pcs_get_state(struct ocelot *ocelot, int port,
52 struct phylink_link_state *state)
53 {
54 - if (ocelot->ops->pcs_link_state)
55 - ocelot->ops->pcs_link_state(ocelot, port, state);
56 - else
57 - state->link = 1;
58 + state->link = 1;
59 }
60 EXPORT_SYMBOL(ocelot_phylink_mac_pcs_get_state);
61
62 void ocelot_phylink_mac_an_restart(struct ocelot *ocelot, int port)
63 {
64 - if (ocelot->ops->pcs_an_restart)
65 - ocelot->ops->pcs_an_restart(ocelot, port);
66 + /* Not supported */
67 }
68 EXPORT_SYMBOL(ocelot_phylink_mac_an_restart);
69
70 @@ -472,7 +490,7 @@ void ocelot_phylink_mac_config(struct oc
71 ocelot_port_writel(ocelot_port, mac_mode, DEV_MAC_MODE_CFG);
72
73 if (ocelot->ops->pcs_init)
74 - ocelot->ops->pcs_init(ocelot, port, link_an_mode, state);
75 + ocelot->ops->pcs_init(ocelot, port);
76
77 /* Enable MAC module */
78 ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
79 --- a/drivers/net/ethernet/mscc/ocelot_board.c
80 +++ b/drivers/net/ethernet/mscc/ocelot_board.c
81 @@ -212,9 +212,7 @@ static const struct of_device_id mscc_oc
82 };
83 MODULE_DEVICE_TABLE(of, mscc_ocelot_match);
84
85 -static void ocelot_port_pcs_init(struct ocelot *ocelot, int port,
86 - unsigned int link_an_mode,
87 - const struct phylink_link_state *state)
88 +static void ocelot_port_pcs_init(struct ocelot *ocelot, int port)
89 {
90 struct ocelot_port *ocelot_port = ocelot->ports[port];
91
92 @@ -237,36 +235,6 @@ static void ocelot_port_pcs_init(struct
93 ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG);
94 }
95
96 -void ocelot_port_pcs_validate(struct ocelot *ocelot, int port,
97 - unsigned long *supported,
98 - struct phylink_link_state *state)
99 -{
100 - __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
101 -
102 - if (state->interface != PHY_INTERFACE_MODE_NA &&
103 - state->interface != PHY_INTERFACE_MODE_GMII &&
104 - state->interface != PHY_INTERFACE_MODE_SGMII &&
105 - state->interface != PHY_INTERFACE_MODE_QSGMII) {
106 - bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
107 - return;
108 - }
109 -
110 - /* No half-duplex. */
111 - phylink_set_port_modes(mask);
112 - phylink_set(mask, Autoneg);
113 - phylink_set(mask, Pause);
114 - phylink_set(mask, Asym_Pause);
115 - phylink_set(mask, 10baseT_Full);
116 - phylink_set(mask, 100baseT_Full);
117 - phylink_set(mask, 1000baseT_Full);
118 - phylink_set(mask, 2500baseT_Full);
119 -
120 - bitmap_and(supported, supported, mask,
121 - __ETHTOOL_LINK_MODE_MASK_NBITS);
122 - bitmap_and(state->advertising, state->advertising, mask,
123 - __ETHTOOL_LINK_MODE_MASK_NBITS);
124 -}
125 -
126 static int ocelot_reset(struct ocelot *ocelot)
127 {
128 int retries = 100;
129 @@ -292,7 +260,6 @@ static int ocelot_reset(struct ocelot *o
130
131 static const struct ocelot_ops ocelot_ops = {
132 .pcs_init = ocelot_port_pcs_init,
133 - .pcs_validate = ocelot_port_pcs_validate,
134 .reset = ocelot_reset,
135 };
136
137 --- a/include/soc/mscc/ocelot.h
138 +++ b/include/soc/mscc/ocelot.h
139 @@ -412,15 +412,7 @@ enum {
140 struct ocelot;
141
142 struct ocelot_ops {
143 - void (*pcs_init)(struct ocelot *ocelot, int port,
144 - unsigned int link_an_mode,
145 - const struct phylink_link_state *state);
146 - void (*pcs_an_restart)(struct ocelot *ocelot, int port);
147 - void (*pcs_link_state)(struct ocelot *ocelot, int port,
148 - struct phylink_link_state *state);
149 - void (*pcs_validate)(struct ocelot *ocelot, int port,
150 - unsigned long *supported,
151 - struct phylink_link_state *state);
152 + void (*pcs_init)(struct ocelot *ocelot, int port);
153 int (*reset)(struct ocelot *ocelot);
154 };
155
156 @@ -487,6 +479,8 @@ struct ocelot {
157 struct mutex ptp_lock;
158 /* Protects the PTP clock */
159 spinlock_t ptp_clock_lock;
160 +
161 + void (*port_pcs_init)(struct ocelot_port *port);
162 };
163
164 #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri))
Staging tree of Daniel Golle