git.openwrt.org Git - openwrt/staging/svanheule.git/blob

   1 From 8aad7c4c5d8becaf6c60e1585c8e70010b3c0ce2 Mon Sep 17 00:00:00 2001
   2 From: Makarand Pawagi <makarand.pawagi@mindspeed.com>
   3 Date: Mon, 2 May 2016 09:33:45 +0530
   4 Subject: [PATCH 19/93] armv8: ls1012a: Add CSU assignment for eSDHC2, SAI1,
   5  SAI2, SAI3, SAI4
   6
   7     Access settings for different IPs has to be enabled through CSU registers. Following
   8     IP's are added for LS1012A:
   9     Added CSU ID for eSDHC-2, reg: CSL40_REG[23:16]
  10     Added CSU ID for SAI-1, reg: CSL41_REG[7:0]
  11     Added CSU ID for SAI-2, reg: CSL41_REG[23:16]
  12     Added CSU ID for SAI-3, reg: CSL42_REG[7:0]
  13     Added CSU ID for SAI-4, reg: CSL42_REG[23:16
  14 ---
  15  .../include/asm/arch-fsl-layerscape/ns_access.h    |   10 ++++++++++
  16  1 file changed, 10 insertions(+)
  17
  18 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
  19 index a3ccdb0..d6642a7 100644
  20 --- a/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
  21 +++ b/arch/arm/include/asm/arch-fsl-layerscape/ns_access.h
  22 @@ -69,7 +69,12 @@ enum csu_cslx_ind {
  23         CSU_CSLX_IIC4 = 77,
  24         CSU_CSLX_WDT4,
  25         CSU_CSLX_WDT3,
  26 +    CSU_CSLX_ESDHC2 = 80,
  27         CSU_CSLX_WDT5 = 81,
  28 +       CSU_CSLX_SAI2,
  29 +       CSU_CSLX_SAI1,
  30 +       CSU_CSLX_SAI4,
  31 +       CSU_CSLX_SAI3,
  32         CSU_CSLX_FTM2 = 86,
  33         CSU_CSLX_FTM1,
  34         CSU_CSLX_FTM4,
  35 @@ -143,7 +148,12 @@ static struct csu_ns_dev ns_dev[] = {
  36          {CSU_CSLX_IIC4, CSU_ALL_RW},
  37          {CSU_CSLX_WDT4, CSU_ALL_RW},
  38          {CSU_CSLX_WDT3, CSU_ALL_RW},
  39 +     {CSU_CSLX_ESDHC2, CSU_ALL_RW},
  40          {CSU_CSLX_WDT5, CSU_ALL_RW},
  41 +        {CSU_CSLX_SAI2, CSU_ALL_RW},
  42 +        {CSU_CSLX_SAI1, CSU_ALL_RW},
  43 +        {CSU_CSLX_SAI4, CSU_ALL_RW},
  44 +        {CSU_CSLX_SAI3, CSU_ALL_RW},
  45          {CSU_CSLX_FTM2, CSU_ALL_RW},
  46          {CSU_CSLX_FTM1, CSU_ALL_RW},
  47          {CSU_CSLX_FTM4, CSU_ALL_RW},
  48 --
  49 1.7.9.5
  50