git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From ef972fc9f5743da589ce9546dd565d6c56e679b8 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Ar=C4=B1n=C3=A7=20=C3=9CNAL?= <arinc.unal@arinc9.com>
   3 Date: Mon, 8 Apr 2024 10:08:53 +0300
   4 Subject: [PATCH 1/2] net: dsa: mt7530: fix enabling EEE on MT7531 switch on
   5  all boards
   6 MIME-Version: 1.0
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   9
  10 The commit 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
  11 brought EEE support but did not enable EEE on MT7531 switch MACs. EEE is
  12 enabled on MT7531 switch MACs by pulling the LAN2LED0 pin low on the board
  13 (bootstrapping), unsetting the EEE_DIS bit on the trap register, or setting
  14 the internal EEE switch bit on the CORE_PLL_GROUP4 register. Thanks to
  15 SkyLake Huang (黃啟澤) from MediaTek for providing information on the
  16 internal EEE switch bit.
  17
  18 There are existing boards that were not designed to pull the pin low.
  19 Because of that, the EEE status currently depends on the board design.
  20
  21 The EEE_DIS bit on the trap pertains to the LAN2LED0 pin which is usually
  22 used to control an LED. Once the bit is unset, the pin will be low. That
  23 will make the active low LED turn on. The pin is controlled by the switch
  24 PHY. It seems that the PHY controls the pin in the way that it inverts the
  25 pin state. That means depending on the wiring of the LED connected to
  26 LAN2LED0 on the board, the LED may be on without an active link.
  27
  28 To not cause this unwanted behaviour whilst enabling EEE on all boards, set
  29 the internal EEE switch bit on the CORE_PLL_GROUP4 register.
  30
  31 My testing on MT7531 shows a certain amount of traffic loss when EEE is
  32 enabled. That said, I haven't come across a board that enables EEE. So
  33 enable EEE on the switch MACs but disable EEE advertisement on the switch
  34 PHYs. This way, we don't change the behaviour of the majority of the boards
  35 that have this switch. The mediatek-ge PHY driver already disables EEE
  36 advertisement on the switch PHYs but my testing shows that it is somehow
  37 enabled afterwards. Disabling EEE advertisement before the PHY driver
  38 initialises keeps it off.
  39
  40 With this change, EEE can now be enabled using ethtool.
  41
  42 Fixes: 40b5d2f15c09 ("net: dsa: mt7530: Add support for EEE features")
  43 Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
  44 Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
  45 ---
  46  drivers/net/dsa/mt7530.c | 17 ++++++++++++-----
  47  drivers/net/dsa/mt7530.h |  1 +
  48  2 files changed, 13 insertions(+), 5 deletions(-)
  49
  50 --- a/drivers/net/dsa/mt7530.c
  51 +++ b/drivers/net/dsa/mt7530.c
  52 @@ -2666,18 +2666,25 @@ mt7531_setup(struct dsa_switch *ds)
  53         mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
  54                    MT7531_GPIO0_INTERRUPT);
  55
  56 -       /* Enable PHY core PLL, since phy_device has not yet been created
  57 -        * provided for phy_[read,write]_mmd_indirect is called, we provide
  58 -        * our own mt7531_ind_mmd_phy_[read,write] to complete this
  59 -        * function.
  60 +       /* Enable Energy-Efficient Ethernet (EEE) and PHY core PLL, since
  61 +        * phy_device has not yet been created provided for
  62 +        * phy_[read,write]_mmd_indirect is called, we provide our own
  63 +        * mt7531_ind_mmd_phy_[read,write] to complete this function.
  64          */
  65         val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
  66                                       MDIO_MMD_VEND2, CORE_PLL_GROUP4);
  67 -       val |= MT7531_PHY_PLL_BYPASS_MODE;
  68 +       val |= MT7531_RG_SYSPLL_DMY2 | MT7531_PHY_PLL_BYPASS_MODE;
  69         val &= ~MT7531_PHY_PLL_OFF;
  70         mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
  71                                  CORE_PLL_GROUP4, val);
  72
  73 +       /* Disable EEE advertisement on the switch PHYs. */
  74 +       for (i = MT753X_CTRL_PHY_ADDR;
  75 +            i < MT753X_CTRL_PHY_ADDR + MT7530_NUM_PHYS; i++) {
  76 +               mt7531_ind_c45_phy_write(priv, i, MDIO_MMD_AN, MDIO_AN_EEE_ADV,
  77 +                                        0);
  78 +       }
  79 +
  80         mt7531_setup_common(ds);
  81
  82         /* Setup VLAN ID 0 for VLAN-unaware bridges */
  83 --- a/drivers/net/dsa/mt7530.h
  84 +++ b/drivers/net/dsa/mt7530.h
  85 @@ -621,6 +621,7 @@ enum mt7531_clk_skew {
  86  #define  RG_SYSPLL_DDSFBK_EN           BIT(12)
  87  #define  RG_SYSPLL_BIAS_EN             BIT(11)
  88  #define  RG_SYSPLL_BIAS_LPF_EN         BIT(10)
  89 +#define  MT7531_RG_SYSPLL_DMY2         BIT(6)
  90  #define  MT7531_PHY_PLL_OFF            BIT(5)
  91  #define  MT7531_PHY_PLL_BYPASS_MODE    BIT(4)
  92