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1 From 244012f3f879d4709be68e7ddabc064268bbd69e Mon Sep 17 00:00:00 2001
2 From: Lei Wei <quic_leiwei@quicinc.com>
3 Date: Thu, 28 Dec 2023 00:38:08 +0800
4 Subject: [PATCH 27/50] net: ethernet: qualcomm: Add PPE L2 bridge
5 initialization
6
7 The per-port L2 bridge settings are initialized as follows:
8 For PPE CPU port, the PPE bridge Tx is enabled and FDB learn is
9 disabled. For PPE physical port, the PPE bridge Tx is disabled
10 and FDB learn is enabled by default and the L2 forward action
11 is initialized as forward to CPU port.
12
13 Change-Id: Ida42464f1d5e53583a434a11b19e6501c649d44e
14 Signed-off-by: Lei Wei <quic_leiwei@quicinc.com>
15 ---
16 .../net/ethernet/qualcomm/ppe/ppe_config.c | 68 ++++++++++++++++++-
17 drivers/net/ethernet/qualcomm/ppe/ppe_regs.h | 54 +++++++++++++++
18 2 files changed, 121 insertions(+), 1 deletion(-)
19
20 diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
21 index a19a6472e4ed..621f4f0ba9e2 100644
22 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
23 +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_config.c
24 @@ -1957,6 +1957,68 @@ static int ppe_queues_to_ring_init(struct ppe_device *ppe_dev)
25 return ppe_ring_queue_map_set(ppe_dev, 0, queue_bmap);
26 }
27
28 +/* Initialize PPE bridge configuration. */
29 +static int ppe_bridge_init(struct ppe_device *ppe_dev)
30 +{
31 + u32 reg, mask, port_cfg[4], vsi_cfg[2];
32 + int ret, i;
33 +
34 + /* CPU port0 enable bridge Tx and disable FDB new address
35 + * learning and station move address learning.
36 + */
37 + mask = PPE_PORT_BRIDGE_TXMAC_EN;
38 + mask |= PPE_PORT_BRIDGE_NEW_LRN_EN;
39 + mask |= PPE_PORT_BRIDGE_STA_MOVE_LRN_EN;
40 + ret = regmap_update_bits(ppe_dev->regmap,
41 + PPE_PORT_BRIDGE_CTRL_ADDR,
42 + mask,
43 + PPE_PORT_BRIDGE_TXMAC_EN);
44 + if (ret)
45 + return ret;
46 +
47 + for (i = 1; i < ppe_dev->num_ports; i++) {
48 + /* Set Invalid VSI forwarding to CPU port0 if no VSI
49 + * is assigned to the port.
50 + */
51 + reg = PPE_L2_VP_PORT_TBL_ADDR + PPE_L2_VP_PORT_TBL_INC * i;
52 + ret = regmap_bulk_read(ppe_dev->regmap, reg,
53 + port_cfg, ARRAY_SIZE(port_cfg));
54 +
55 + if (ret)
56 + return ret;
57 +
58 + PPE_L2_PORT_SET_INVALID_VSI_FWD_EN(port_cfg, true);
59 + PPE_L2_PORT_SET_DST_INFO(port_cfg, 0);
60 +
61 + ret = regmap_bulk_write(ppe_dev->regmap, reg,
62 + port_cfg, ARRAY_SIZE(port_cfg));
63 + if (ret)
64 + return ret;
65 + }
66 +
67 + for (i = 0; i < PPE_VSI_TBL_NUM; i++) {
68 + /* Enable VSI bridge forward address learning and set VSI
69 + * forward member includes CPU port0.
70 + */
71 + PPE_VSI_SET_MEMBER_PORT_BITMAP(vsi_cfg, BIT(0));
72 + PPE_VSI_SET_UUC_BITMAP(vsi_cfg, BIT(0));
73 + PPE_VSI_SET_UMC_BITMAP(vsi_cfg, BIT(0));
74 + PPE_VSI_SET_BC_BITMAP(vsi_cfg, BIT(0));
75 + PPE_VSI_SET_NEW_ADDR_LRN_EN(vsi_cfg, true);
76 + PPE_VSI_SET_NEW_ADDR_FWD_CMD(vsi_cfg, PPE_ACTION_FORWARD);
77 + PPE_VSI_SET_STATION_MOVE_LRN_EN(vsi_cfg, true);
78 + PPE_VSI_SET_STATION_MOVE_FWD_CMD(vsi_cfg, PPE_ACTION_FORWARD);
79 +
80 + reg = PPE_VSI_TBL_ADDR + PPE_VSI_TBL_INC * i;
81 + ret = regmap_bulk_write(ppe_dev->regmap, reg,
82 + vsi_cfg, ARRAY_SIZE(vsi_cfg));
83 + if (ret)
84 + return ret;
85 + }
86 +
87 + return 0;
88 +}
89 +
90 /* Initialize PPE device to handle traffic correctly. */
91 static int ppe_dev_hw_init(struct ppe_device *ppe_dev)
92 {
93 @@ -1978,7 +2040,11 @@ static int ppe_dev_hw_init(struct ppe_device *ppe_dev)
94 if (ret)
95 return ret;
96
97 - return ppe_queues_to_ring_init(ppe_dev);
98 + ret = ppe_queues_to_ring_init(ppe_dev);
99 + if (ret)
100 + return ret;
101 +
102 + return ppe_bridge_init(ppe_dev);
103 }
104
105 int ppe_hw_config(struct ppe_device *ppe_dev)
106 diff --git a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
107 index 8c6cd6b52b0f..7f06843e4151 100644
108 --- a/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
109 +++ b/drivers/net/ethernet/qualcomm/ppe/ppe_regs.h
110 @@ -126,6 +126,18 @@
111 #define PPE_EG_SERVICE_SET_TX_CNT_EN(tbl_cfg, value) \
112 u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_EG_SERVICE_W1_TX_CNT_EN)
113
114 +/* PPE port bridge configuration */
115 +#define PPE_PORT_BRIDGE_CTRL_ADDR 0x60300
116 +#define PPE_PORT_BRIDGE_CTRL_NUM 8
117 +#define PPE_PORT_BRIDGE_CTRL_INC 4
118 +#define PPE_PORT_BRIDGE_NEW_LRN_EN BIT(0)
119 +#define PPE_PORT_BRIDGE_NEW_FWD_CMD GENMASK(2, 1)
120 +#define PPE_PORT_BRIDGE_STA_MOVE_LRN_EN BIT(3)
121 +#define PPE_PORT_BRIDGE_STA_MOVE_FWD_CMD GENMASK(5, 4)
122 +#define PPE_PORT_BRIDGE_ISOLATION_BITMAP GENMASK(15, 8)
123 +#define PPE_PORT_BRIDGE_TXMAC_EN BIT(16)
124 +#define PPE_PORT_BRIDGE_PROMISC_EN BIT(17)
125 +
126 #define PPE_MC_MTU_CTRL_TBL_ADDR 0x60a00
127 #define PPE_MC_MTU_CTRL_TBL_NUM 8
128 #define PPE_MC_MTU_CTRL_TBL_INC 4
129 @@ -133,6 +145,36 @@
130 #define PPE_MC_MTU_CTRL_TBL_MTU_CMD GENMASK(15, 14)
131 #define PPE_MC_MTU_CTRL_TBL_TX_CNT_EN BIT(16)
132
133 +/* PPE VSI configurations */
134 +#define PPE_VSI_TBL_ADDR 0x63800
135 +#define PPE_VSI_TBL_NUM 64
136 +#define PPE_VSI_TBL_INC 0x10
137 +#define PPE_VSI_W0_MEMBER_PORT_BITMAP GENMASK(7, 0)
138 +#define PPE_VSI_W0_UUC_BITMAP GENMASK(15, 8)
139 +#define PPE_VSI_W0_UMC_BITMAP GENMASK(23, 16)
140 +#define PPE_VSI_W0_BC_BITMAP GENMASK(31, 24)
141 +#define PPE_VSI_W1_NEW_ADDR_LRN_EN BIT(0)
142 +#define PPE_VSI_W1_NEW_ADDR_FWD_CMD GENMASK(2, 1)
143 +#define PPE_VSI_W1_STATION_MOVE_LRN_EN BIT(3)
144 +#define PPE_VSI_W1_STATION_MOVE_FWD_CMD GENMASK(5, 4)
145 +
146 +#define PPE_VSI_SET_MEMBER_PORT_BITMAP(tbl_cfg, value) \
147 + u32p_replace_bits((u32 *)tbl_cfg, value, PPE_VSI_W0_MEMBER_PORT_BITMAP)
148 +#define PPE_VSI_SET_UUC_BITMAP(tbl_cfg, value) \
149 + u32p_replace_bits((u32 *)tbl_cfg, value, PPE_VSI_W0_UUC_BITMAP)
150 +#define PPE_VSI_SET_UMC_BITMAP(tbl_cfg, value) \
151 + u32p_replace_bits((u32 *)tbl_cfg, value, PPE_VSI_W0_UMC_BITMAP)
152 +#define PPE_VSI_SET_BC_BITMAP(tbl_cfg, value) \
153 + u32p_replace_bits((u32 *)tbl_cfg, value, PPE_VSI_W0_BC_BITMAP)
154 +#define PPE_VSI_SET_NEW_ADDR_LRN_EN(tbl_cfg, value) \
155 + u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_VSI_W1_NEW_ADDR_LRN_EN)
156 +#define PPE_VSI_SET_NEW_ADDR_FWD_CMD(tbl_cfg, value) \
157 + u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_VSI_W1_NEW_ADDR_FWD_CMD)
158 +#define PPE_VSI_SET_STATION_MOVE_LRN_EN(tbl_cfg, value) \
159 + u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_VSI_W1_STATION_MOVE_LRN_EN)
160 +#define PPE_VSI_SET_STATION_MOVE_FWD_CMD(tbl_cfg, value) \
161 + u32p_replace_bits((u32 *)(tbl_cfg) + 0x1, value, PPE_VSI_W1_STATION_MOVE_FWD_CMD)
162 +
163 /* PPE port control configuration, the MTU and MRU configs. */
164 #define PPE_MRU_MTU_CTRL_TBL_ADDR 0x65000
165 #define PPE_MRU_MTU_CTRL_TBL_NUM 256
166 @@ -170,6 +212,18 @@
167 #define PPE_IN_L2_SERVICE_TBL_RX_CNT_EN BIT(30)
168 #define PPE_IN_L2_SERVICE_TBL_TX_CNT_EN BIT(31)
169
170 +/* L2 Port configurations */
171 +#define PPE_L2_VP_PORT_TBL_ADDR 0x98000
172 +#define PPE_L2_VP_PORT_TBL_NUM 256
173 +#define PPE_L2_VP_PORT_TBL_INC 0x10
174 +#define PPE_L2_VP_PORT_W0_INVALID_VSI_FWD_EN BIT(0)
175 +#define PPE_L2_VP_PORT_W0_DST_INFO GENMASK(9, 2)
176 +
177 +#define PPE_L2_PORT_SET_INVALID_VSI_FWD_EN(tbl_cfg, value) \
178 + u32p_replace_bits((u32 *)tbl_cfg, value, PPE_L2_VP_PORT_W0_INVALID_VSI_FWD_EN)
179 +#define PPE_L2_PORT_SET_DST_INFO(tbl_cfg, value) \
180 + u32p_replace_bits((u32 *)tbl_cfg, value, PPE_L2_VP_PORT_W0_DST_INFO)
181 +
182 #define PPE_TL_SERVICE_TBL_ADDR 0x306000
183 #define PPE_TL_SERVICE_TBL_NUM 256
184 #define PPE_TL_SERVICE_TBL_INC 4
185 --
186 2.45.2
187
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