git.openwrt.org Git - openwrt/staging/ynezz.git/blob

   1 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   2 Date: Tue, 27 Jun 2017 19:35:27 +0200
   3 Subject: [PATCH] ARM: dts: BCM5301X: Specify USB ports for each controller
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   7
   8 Northstar has 3 controllers: OHCI and EHCI (each with 2 ports) and XHCI
   9 (with just 1 port). Describe them in the DT. In future this will allow
  10 to reference them as trigger sources.
  11
  12 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  13 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  14 ---
  15  arch/arm/boot/dts/bcm5301x.dtsi | 34 ++++++++++++++++++++++++++++++++++
  16  1 file changed, 34 insertions(+)
  17
  18 --- a/arch/arm/boot/dts/bcm5301x.dtsi
  19 +++ b/arch/arm/boot/dts/bcm5301x.dtsi
  20 @@ -272,6 +272,19 @@
  21                                 reg = <0x00021000 0x1000>;
  22                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  23                                 phys = <&usb2_phy>;
  24 +
  25 +                               #address-cells = <1>;
  26 +                               #size-cells = <0>;
  27 +
  28 +                               ehci_port1: port@1 {
  29 +                                       reg = <1>;
  30 +                                       #trigger-source-cells = <0>;
  31 +                               };
  32 +
  33 +                               ehci_port2: port@2 {
  34 +                                       reg = <2>;
  35 +                                       #trigger-source-cells = <0>;
  36 +                               };
  37                         };
  38
  39                         ohci: ohci@22000 {
  40 @@ -280,6 +293,19 @@
  41                                 compatible = "generic-ohci";
  42                                 reg = <0x00022000 0x1000>;
  43                                 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
  44 +
  45 +                               #address-cells = <1>;
  46 +                               #size-cells = <0>;
  47 +
  48 +                               ohci_port1: port@1 {
  49 +                                       reg = <1>;
  50 +                                       #trigger-source-cells = <0>;
  51 +                               };
  52 +
  53 +                               ohci_port2: port@2 {
  54 +                                       reg = <2>;
  55 +                                       #trigger-source-cells = <0>;
  56 +                               };
  57                         };
  58                 };
  59
  60 @@ -300,6 +326,14 @@
  61                                 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
  62                                 phys = <&usb3_phy>;
  63                                 phy-names = "usb";
  64 +
  65 +                               #address-cells = <1>;
  66 +                               #size-cells = <0>;
  67 +
  68 +                               xhci_port1: port@1 {
  69 +                                       reg = <1>;
  70 +                                       #trigger-source-cells = <0>;
  71 +                               };
  72                         };
  73                 };
  74