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1 From: Md Sadre Alam <quic_mdalam@quicinc.com>
2 Date: Sun, 22 Sep 2024 17:03:49 +0530
3 Subject: [PATCH] spi: spi-qpic: add driver for QCOM SPI NAND flash Interface
4
5 This driver implements support for the SPI-NAND mode of QCOM NAND Flash
6 Interface as a SPI-MEM controller with pipelined ECC capability.
7
8 Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
9 Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
10 Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
11 Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
12 Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
13 ---
14 --- a/drivers/mtd/nand/Makefile
15 +++ b/drivers/mtd/nand/Makefile
16 @@ -7,8 +7,11 @@ obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bm
17
18 ifeq ($(CONFIG_MTD_NAND_QCOM),y)
19 obj-y += qpic_common.o
20 +else
21 +ifeq ($(CONFIG_SPI_QPIC_SNAND),y)
22 +obj-y += qpic_common.o
23 +endif
24 endif
25 -
26 obj-y += onenand/
27 obj-y += raw/
28 obj-y += spi/
29 --- a/drivers/spi/Kconfig
30 +++ b/drivers/spi/Kconfig
31 @@ -870,6 +870,14 @@ config SPI_QCOM_QSPI
32 help
33 QSPI(Quad SPI) driver for Qualcomm QSPI controller.
34
35 +config SPI_QPIC_SNAND
36 + bool "QPIC SNAND controller"
37 + depends on ARCH_QCOM || COMPILE_TEST
38 + help
39 + QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller.
40 + QPIC controller supports both parallel nand and serial nand.
41 + This config will enable serial nand driver for QPIC controller.
42 +
43 config SPI_QUP
44 tristate "Qualcomm SPI controller with QUP interface"
45 depends on ARCH_QCOM || COMPILE_TEST
46 --- a/drivers/spi/Makefile
47 +++ b/drivers/spi/Makefile
48 @@ -110,6 +110,7 @@ obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-
49 obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
50 obj-$(CONFIG_SPI_QCOM_GENI) += spi-geni-qcom.o
51 obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o
52 +obj-$(CONFIG_SPI_QPIC_SNAND) += spi-qpic-snand.o
53 obj-$(CONFIG_SPI_QUP) += spi-qup.o
54 obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
55 obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o
56 --- /dev/null
57 +++ b/drivers/spi/spi-qpic-snand.c
58 @@ -0,0 +1,1634 @@
59 +/*
60 + * SPDX-License-Identifier: GPL-2.0
61 + *
62 + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
63 + *
64 + * Authors:
65 + * Md Sadre Alam <quic_mdalam@quicinc.com>
66 + * Sricharan R <quic_srichara@quicinc.com>
67 + * Varadarajan Narayanan <quic_varada@quicinc.com>
68 + */
69 +#include <linux/bitops.h>
70 +#include <linux/clk.h>
71 +#include <linux/delay.h>
72 +#include <linux/dmaengine.h>
73 +#include <linux/dma-mapping.h>
74 +#include <linux/dma/qcom_adm.h>
75 +#include <linux/dma/qcom_bam_dma.h>
76 +#include <linux/module.h>
77 +#include <linux/of.h>
78 +#include <linux/platform_device.h>
79 +#include <linux/slab.h>
80 +#include <linux/mtd/nand-qpic-common.h>
81 +#include <linux/mtd/spinand.h>
82 +#include <linux/bitfield.h>
83 +
84 +#define NAND_FLASH_SPI_CFG 0xc0
85 +#define NAND_NUM_ADDR_CYCLES 0xc4
86 +#define NAND_BUSY_CHECK_WAIT_CNT 0xc8
87 +#define NAND_FLASH_FEATURES 0xf64
88 +
89 +/* QSPI NAND config reg bits */
90 +#define LOAD_CLK_CNTR_INIT_EN BIT(28)
91 +#define CLK_CNTR_INIT_VAL_VEC 0x924
92 +#define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16)
93 +#define FEA_STATUS_DEV_ADDR 0xc0
94 +#define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8)
95 +#define SPI_CFG BIT(0)
96 +#define SPI_NUM_ADDR 0xDA4DB
97 +#define SPI_WAIT_CNT 0x10
98 +#define QPIC_QSPI_NUM_CS 1
99 +#define SPI_TRANSFER_MODE_x1 BIT(29)
100 +#define SPI_TRANSFER_MODE_x4 (3 << 29)
101 +#define SPI_WP BIT(28)
102 +#define SPI_HOLD BIT(27)
103 +#define QPIC_SET_FEATURE BIT(31)
104 +
105 +#define SPINAND_RESET 0xff
106 +#define SPINAND_READID 0x9f
107 +#define SPINAND_GET_FEATURE 0x0f
108 +#define SPINAND_SET_FEATURE 0x1f
109 +#define SPINAND_READ 0x13
110 +#define SPINAND_ERASE 0xd8
111 +#define SPINAND_WRITE_EN 0x06
112 +#define SPINAND_PROGRAM_EXECUTE 0x10
113 +#define SPINAND_PROGRAM_LOAD 0x84
114 +
115 +#define ACC_FEATURE 0xe
116 +#define BAD_BLOCK_MARKER_SIZE 0x2
117 +#define OOB_BUF_SIZE 128
118 +#define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng)
119 +struct qpic_snand_op {
120 + u32 cmd_reg;
121 + u32 addr1_reg;
122 + u32 addr2_reg;
123 +};
124 +
125 +struct snandc_read_status {
126 + __le32 snandc_flash;
127 + __le32 snandc_buffer;
128 + __le32 snandc_erased_cw;
129 +};
130 +
131 +/*
132 + * ECC state struct
133 + * @corrected: ECC corrected
134 + * @bitflips: Max bit flip
135 + * @failed: ECC failed
136 + */
137 +struct qcom_ecc_stats {
138 + u32 corrected;
139 + u32 bitflips;
140 + u32 failed;
141 +};
142 +
143 +struct qpic_ecc {
144 + struct device *dev;
145 + int ecc_bytes_hw;
146 + int spare_bytes;
147 + int bbm_size;
148 + int ecc_mode;
149 + int bytes;
150 + int steps;
151 + int step_size;
152 + int strength;
153 + int cw_size;
154 + int cw_data;
155 + u32 cfg0;
156 + u32 cfg1;
157 + u32 cfg0_raw;
158 + u32 cfg1_raw;
159 + u32 ecc_buf_cfg;
160 + u32 ecc_bch_cfg;
161 + u32 clrflashstatus;
162 + u32 clrreadstatus;
163 + bool bch_enabled;
164 +};
165 +
166 +struct qpic_spi_nand {
167 + struct qcom_nand_controller *snandc;
168 + struct spi_controller *ctlr;
169 + struct mtd_info *mtd;
170 + struct clk *iomacro_clk;
171 + struct qpic_ecc *ecc;
172 + struct qcom_ecc_stats ecc_stats;
173 + struct nand_ecc_engine ecc_eng;
174 + u8 *data_buf;
175 + u8 *oob_buf;
176 + u32 wlen;
177 + __le32 addr1;
178 + __le32 addr2;
179 + __le32 cmd;
180 + u32 num_cw;
181 + bool oob_rw;
182 + bool page_rw;
183 + bool raw_rw;
184 +};
185 +
186 +static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
187 + int reg, int cw_offset, int read_size,
188 + int is_last_read_loc)
189 +{
190 + __le32 locreg_val;
191 + u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
192 + ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)
193 + << READ_LOCATION_LAST));
194 +
195 + locreg_val = cpu_to_le32(val);
196 +
197 + if (reg == NAND_READ_LOCATION_0)
198 + snandc->regs->read_location0 = locreg_val;
199 + else if (reg == NAND_READ_LOCATION_1)
200 + snandc->regs->read_location1 = locreg_val;
201 + else if (reg == NAND_READ_LOCATION_2)
202 + snandc->regs->read_location1 = locreg_val;
203 + else if (reg == NAND_READ_LOCATION_3)
204 + snandc->regs->read_location3 = locreg_val;
205 +}
206 +
207 +static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc,
208 + int reg, int cw_offset, int read_size,
209 + int is_last_read_loc)
210 +{
211 + __le32 locreg_val;
212 + u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
213 + ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)
214 + << READ_LOCATION_LAST));
215 +
216 + locreg_val = cpu_to_le32(val);
217 +
218 + if (reg == NAND_READ_LOCATION_LAST_CW_0)
219 + snandc->regs->read_location_last0 = locreg_val;
220 + else if (reg == NAND_READ_LOCATION_LAST_CW_1)
221 + snandc->regs->read_location_last1 = locreg_val;
222 + else if (reg == NAND_READ_LOCATION_LAST_CW_2)
223 + snandc->regs->read_location_last2 = locreg_val;
224 + else if (reg == NAND_READ_LOCATION_LAST_CW_3)
225 + snandc->regs->read_location_last3 = locreg_val;
226 +}
227 +
228 +static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand)
229 +{
230 + struct nand_ecc_engine *eng = nand->ecc.engine;
231 + struct qpic_spi_nand *qspi = ecceng_to_qspi(eng);
232 +
233 + return qspi->snandc;
234 +}
235 +
236 +static int qcom_spi_init(struct qcom_nand_controller *snandc)
237 +{
238 + u32 snand_cfg_val = 0x0;
239 + int ret;
240 +
241 + snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) |
242 + FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) |
243 + FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) |
244 + FIELD_PREP(SPI_CFG, 0);
245 +
246 + snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
247 + snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR);
248 + snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT);
249 +
250 + qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
251 +
252 + snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
253 + snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
254 +
255 + qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
256 +
257 + qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0);
258 + qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1,
259 + NAND_BAM_NEXT_SGL);
260 +
261 + ret = qcom_submit_descs(snandc);
262 + if (ret) {
263 + dev_err(snandc->dev, "failure in submitting spi init descriptor\n");
264 + return ret;
265 + }
266 +
267 + return ret;
268 +}
269 +
270 +static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section,
271 + struct mtd_oob_region *oobregion)
272 +{
273 + struct nand_device *nand = mtd_to_nanddev(mtd);
274 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
275 + struct qpic_ecc *qecc = snandc->qspi->ecc;
276 +
277 + if (section > 1)
278 + return -ERANGE;
279 +
280 + oobregion->length = qecc->ecc_bytes_hw + qecc->spare_bytes;
281 + oobregion->offset = mtd->oobsize - oobregion->length;
282 +
283 + return 0;
284 +}
285 +
286 +static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section,
287 + struct mtd_oob_region *oobregion)
288 +{
289 + struct nand_device *nand = mtd_to_nanddev(mtd);
290 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
291 + struct qpic_ecc *qecc = snandc->qspi->ecc;
292 +
293 + if (section)
294 + return -ERANGE;
295 +
296 + oobregion->length = qecc->steps * 4;
297 + oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size;
298 +
299 + return 0;
300 +}
301 +
302 +static const struct mtd_ooblayout_ops qcom_spi_ooblayout = {
303 + .ecc = qcom_spi_ooblayout_ecc,
304 + .free = qcom_spi_ooblayout_free,
305 +};
306 +
307 +static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
308 +{
309 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
310 + struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
311 + struct mtd_info *mtd = nanddev_to_mtd(nand);
312 + int cwperpage, bad_block_byte;
313 + struct qpic_ecc *ecc_cfg;
314 +
315 + cwperpage = mtd->writesize / NANDC_STEP_SIZE;
316 + snandc->qspi->num_cw = cwperpage;
317 +
318 + ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
319 + if (!ecc_cfg)
320 + return -ENOMEM;
321 + snandc->qspi->oob_buf = kzalloc(mtd->writesize + mtd->oobsize,
322 + GFP_KERNEL);
323 + if (!snandc->qspi->oob_buf)
324 + return -ENOMEM;
325 +
326 + memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize);
327 +
328 + nand->ecc.ctx.priv = ecc_cfg;
329 + snandc->qspi->mtd = mtd;
330 +
331 + ecc_cfg->ecc_bytes_hw = 7;
332 + ecc_cfg->spare_bytes = 4;
333 + ecc_cfg->bbm_size = 1;
334 + ecc_cfg->bch_enabled = true;
335 + ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
336 +
337 + ecc_cfg->steps = 4;
338 + ecc_cfg->strength = 4;
339 + ecc_cfg->step_size = 512;
340 + ecc_cfg->cw_data = 516;
341 + ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
342 + bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
343 +
344 + mtd_set_ooblayout(mtd, &qcom_spi_ooblayout);
345 +
346 + ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
347 + FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) |
348 + FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) |
349 + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
350 + FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) |
351 + FIELD_PREP(STATUS_BFR_READ, 0) |
352 + FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
353 + FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes);
354 +
355 + ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
356 + FIELD_PREP(CS_ACTIVE_BSY, 0) |
357 + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
358 + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
359 + FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
360 + FIELD_PREP(WIDE_FLASH, 0) |
361 + FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled);
362 +
363 + ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
364 + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
365 + FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) |
366 + FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
367 +
368 + ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
369 + FIELD_PREP(CS_ACTIVE_BSY, 0) |
370 + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
371 + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
372 + FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
373 + FIELD_PREP(WIDE_FLASH, 0) |
374 + FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
375 +
376 + ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) |
377 + FIELD_PREP(ECC_SW_RESET, 0) |
378 + FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
379 + FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
380 + FIELD_PREP(ECC_MODE_MASK, 0) |
381 + FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
382 +
383 + ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS;
384 + ecc_cfg->clrflashstatus = FS_READY_BSY_N;
385 + ecc_cfg->clrreadstatus = 0xc0;
386 +
387 + conf->step_size = ecc_cfg->step_size;
388 + conf->strength = ecc_cfg->strength;
389 +
390 + snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET);
391 + snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET);
392 +
393 + dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n",
394 + ecc_cfg->strength, ecc_cfg->step_size);
395 +
396 + return 0;
397 +}
398 +
399 +static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand)
400 +{
401 + struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
402 +
403 + kfree(ecc_cfg);
404 +}
405 +
406 +static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand,
407 + struct nand_page_io_req *req)
408 +{
409 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
410 + struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
411 +
412 + snandc->qspi->ecc = ecc_cfg;
413 + snandc->qspi->raw_rw = false;
414 + snandc->qspi->oob_rw = false;
415 + snandc->qspi->page_rw = false;
416 +
417 + if (req->datalen)
418 + snandc->qspi->page_rw = true;
419 +
420 + if (req->ooblen)
421 + snandc->qspi->oob_rw = true;
422 +
423 + if (req->mode == MTD_OPS_RAW)
424 + snandc->qspi->raw_rw = true;
425 +
426 + return 0;
427 +}
428 +
429 +static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand,
430 + struct nand_page_io_req *req)
431 +{
432 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
433 + struct mtd_info *mtd = nanddev_to_mtd(nand);
434 +
435 + if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ)
436 + return 0;
437 +
438 + if (snandc->qspi->ecc_stats.failed)
439 + mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed;
440 + else
441 + mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected;
442 +
443 + if (snandc->qspi->ecc_stats.failed)
444 + return -EBADMSG;
445 + else
446 + return snandc->qspi->ecc_stats.bitflips;
447 +}
448 +
449 +static struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = {
450 + .init_ctx = qcom_spi_ecc_init_ctx_pipelined,
451 + .cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined,
452 + .prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined,
453 + .finish_io_req = qcom_spi_ecc_finish_io_req_pipelined,
454 +};
455 +
456 +/* helper to configure location register values */
457 +static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg,
458 + int cw_offset, int read_size, int is_last_read_loc)
459 +{
460 + int reg_base = NAND_READ_LOCATION_0;
461 + int num_cw = snandc->qspi->num_cw;
462 +
463 + if (cw == (num_cw - 1))
464 + reg_base = NAND_READ_LOCATION_LAST_CW_0;
465 +
466 + reg_base += reg * 4;
467 +
468 + if (cw == (num_cw - 1))
469 + return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset,
470 + read_size, is_last_read_loc);
471 + else
472 + return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset,
473 + read_size, is_last_read_loc);
474 +}
475 +
476 +static void
477 +qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw)
478 +{
479 + __le32 *reg = &snandc->regs->read_location0;
480 + int num_cw = snandc->qspi->num_cw;
481 +
482 + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
483 + if (cw == (num_cw - 1)) {
484 + reg = &snandc->regs->read_location_last0;
485 + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4,
486 + NAND_BAM_NEXT_SGL);
487 + }
488 +
489 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
490 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
491 +
492 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
493 + qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
494 + NAND_BAM_NEXT_SGL);
495 +}
496 +
497 +static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)
498 +{
499 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
500 + int ret;
501 +
502 + snandc->buf_count = 0;
503 + snandc->buf_start = 0;
504 + qcom_clear_read_regs(snandc);
505 + qcom_clear_bam_transaction(snandc);
506 +
507 + snandc->regs->cmd = snandc->qspi->cmd;
508 + snandc->regs->addr0 = snandc->qspi->addr1;
509 + snandc->regs->addr1 = snandc->qspi->addr2;
510 + snandc->regs->cfg0 = cpu_to_le32(ecc_cfg->cfg0_raw & ~(7 << CW_PER_PAGE));
511 + snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw);
512 + snandc->regs->exec = cpu_to_le32(1);
513 +
514 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
515 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
516 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
517 +
518 + ret = qcom_submit_descs(snandc);
519 + if (ret) {
520 + dev_err(snandc->dev, "failure to erase block\n");
521 + return ret;
522 + }
523 +
524 + return 0;
525 +}
526 +
527 +static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc,
528 + bool use_ecc, int cw)
529 +{
530 + __le32 *reg = &snandc->regs->read_location0;
531 + int num_cw = snandc->qspi->num_cw;
532 +
533 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
534 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
535 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
536 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
537 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
538 + NAND_ERASED_CW_DETECT_CFG, 1,
539 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
540 +
541 + if (cw == (num_cw - 1)) {
542 + reg = &snandc->regs->read_location_last0;
543 + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL);
544 + }
545 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
546 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
547 +
548 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0);
549 +}
550 +
551 +static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc,
552 + const struct spi_mem_op *op)
553 +{
554 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
555 + struct mtd_info *mtd = snandc->qspi->mtd;
556 + int size, ret = 0;
557 + int col, bbpos;
558 + u32 cfg0, cfg1, ecc_bch_cfg;
559 + u32 num_cw = snandc->qspi->num_cw;
560 +
561 + qcom_clear_bam_transaction(snandc);
562 + qcom_clear_read_regs(snandc);
563 +
564 + size = ecc_cfg->cw_size;
565 + col = ecc_cfg->cw_size * (num_cw - 1);
566 +
567 + memset(snandc->data_buffer, 0xff, size);
568 + snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
569 + snandc->regs->addr1 = snandc->qspi->addr2;
570 +
571 + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
572 + 0 << CW_PER_PAGE;
573 + cfg1 = ecc_cfg->cfg1_raw;
574 + ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
575 +
576 + snandc->regs->cmd = snandc->qspi->cmd;
577 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
578 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
579 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
580 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
581 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
582 + snandc->regs->exec = cpu_to_le32(1);
583 +
584 + qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1);
585 +
586 + qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1);
587 +
588 + qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0);
589 +
590 + ret = qcom_submit_descs(snandc);
591 + if (ret) {
592 + dev_err(snandc->dev, "failed to read last cw\n");
593 + return ret;
594 + }
595 +
596 + qcom_nandc_dev_to_mem(snandc, true);
597 + u32 flash = le32_to_cpu(snandc->reg_read_buf[0]);
598 +
599 + if (flash & (FS_OP_ERR | FS_MPU_ERR))
600 + return -EIO;
601 +
602 + bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
603 +
604 + if (snandc->data_buffer[bbpos] == 0xff)
605 + snandc->data_buffer[bbpos + 1] = 0xff;
606 + if (snandc->data_buffer[bbpos] != 0xff)
607 + snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos];
608 +
609 + memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes);
610 +
611 + return ret;
612 +}
613 +
614 +static int qcom_spi_check_error(struct qcom_nand_controller *snandc, u8 *data_buf, u8 *oob_buf)
615 +{
616 + struct snandc_read_status *buf;
617 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
618 + int i, num_cw = snandc->qspi->num_cw;
619 + bool flash_op_err = false, erased;
620 + unsigned int max_bitflips = 0;
621 + unsigned int uncorrectable_cws = 0;
622 +
623 + snandc->qspi->ecc_stats.failed = 0;
624 + snandc->qspi->ecc_stats.corrected = 0;
625 +
626 + qcom_nandc_dev_to_mem(snandc, true);
627 + buf = (struct snandc_read_status *)snandc->reg_read_buf;
628 +
629 + for (i = 0; i < num_cw; i++, buf++) {
630 + u32 flash, buffer, erased_cw;
631 + int data_len, oob_len;
632 +
633 + if (i == (num_cw - 1)) {
634 + data_len = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
635 + oob_len = num_cw << 2;
636 + } else {
637 + data_len = ecc_cfg->cw_data;
638 + oob_len = 0;
639 + }
640 +
641 + flash = le32_to_cpu(buf->snandc_flash);
642 + buffer = le32_to_cpu(buf->snandc_buffer);
643 + erased_cw = le32_to_cpu(buf->snandc_erased_cw);
644 +
645 + if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) {
646 + if (ecc_cfg->bch_enabled)
647 + erased = (erased_cw & ERASED_CW) == ERASED_CW;
648 + else
649 + erased = false;
650 +
651 + if (!erased)
652 + uncorrectable_cws |= BIT(i);
653 +
654 + } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
655 + flash_op_err = true;
656 + } else {
657 + unsigned int stat;
658 +
659 + stat = buffer & BS_CORRECTABLE_ERR_MSK;
660 + snandc->qspi->ecc_stats.corrected += stat;
661 + max_bitflips = max(max_bitflips, stat);
662 + }
663 +
664 + if (data_buf)
665 + data_buf += data_len;
666 + if (oob_buf)
667 + oob_buf += oob_len + ecc_cfg->bytes;
668 + }
669 +
670 + if (flash_op_err)
671 + return -EIO;
672 +
673 + if (!uncorrectable_cws)
674 + snandc->qspi->ecc_stats.bitflips = max_bitflips;
675 + else
676 + snandc->qspi->ecc_stats.failed++;
677 +
678 + return 0;
679 +}
680 +
681 +static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt)
682 +{
683 + int i;
684 +
685 + qcom_nandc_dev_to_mem(snandc, true);
686 +
687 + for (i = 0; i < cw_cnt; i++) {
688 + u32 flash = le32_to_cpu(snandc->reg_read_buf[i]);
689 +
690 + if (flash & (FS_OP_ERR | FS_MPU_ERR))
691 + return -EIO;
692 + }
693 +
694 + return 0;
695 +}
696 +
697 +static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf,
698 + u8 *oob_buf, int cw)
699 +{
700 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
701 + struct mtd_info *mtd = snandc->qspi->mtd;
702 + int data_size1, data_size2, oob_size1, oob_size2;
703 + int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
704 + int raw_cw = cw;
705 + u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
706 + int col;
707 +
708 + snandc->buf_count = 0;
709 + snandc->buf_start = 0;
710 + qcom_clear_read_regs(snandc);
711 + qcom_clear_bam_transaction(snandc);
712 + raw_cw = num_cw - 1;
713 +
714 + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
715 + 0 << CW_PER_PAGE;
716 + cfg1 = ecc_cfg->cfg1_raw;
717 + ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
718 +
719 + col = ecc_cfg->cw_size * cw;
720 +
721 + snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
722 + snandc->regs->addr1 = snandc->qspi->addr2;
723 + snandc->regs->cmd = snandc->qspi->cmd;
724 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
725 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
726 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
727 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
728 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
729 + snandc->regs->exec = cpu_to_le32(1);
730 +
731 + qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1);
732 +
733 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
734 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
735 + qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
736 +
737 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
738 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
739 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
740 + NAND_ERASED_CW_DETECT_CFG, 1,
741 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
742 +
743 + data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
744 + oob_size1 = ecc_cfg->bbm_size;
745 +
746 + if (cw == (num_cw - 1)) {
747 + data_size2 = NANDC_STEP_SIZE - data_size1 -
748 + ((num_cw - 1) * 4);
749 + oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw +
750 + ecc_cfg->spare_bytes;
751 + } else {
752 + data_size2 = ecc_cfg->cw_data - data_size1;
753 + oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
754 + }
755 +
756 + qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0);
757 + read_loc += data_size1;
758 +
759 + qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0);
760 + read_loc += oob_size1;
761 +
762 + qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0);
763 + read_loc += data_size2;
764 +
765 + qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1);
766 +
767 + qcom_spi_config_cw_read(snandc, false, raw_cw);
768 +
769 + qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0);
770 + reg_off += data_size1;
771 +
772 + qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0);
773 + reg_off += oob_size1;
774 +
775 + qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0);
776 + reg_off += data_size2;
777 +
778 + qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
779 +
780 + ret = qcom_submit_descs(snandc);
781 + if (ret) {
782 + dev_err(snandc->dev, "failure to read raw cw %d\n", cw);
783 + return ret;
784 + }
785 +
786 + return qcom_spi_check_raw_flash_errors(snandc, 1);
787 +}
788 +
789 +static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc,
790 + const struct spi_mem_op *op)
791 +{
792 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
793 + u8 *data_buf = NULL, *oob_buf = NULL;
794 + int ret, cw;
795 + u32 num_cw = snandc->qspi->num_cw;
796 +
797 + if (snandc->qspi->page_rw)
798 + data_buf = op->data.buf.in;
799 +
800 + oob_buf = snandc->qspi->oob_buf;
801 + memset(oob_buf, 0xff, OOB_BUF_SIZE);
802 +
803 + for (cw = 0; cw < num_cw; cw++) {
804 + ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw);
805 + if (ret)
806 + return ret;
807 +
808 + if (data_buf)
809 + data_buf += ecc_cfg->cw_data;
810 + if (oob_buf)
811 + oob_buf += ecc_cfg->bytes;
812 + }
813 +
814 + return 0;
815 +}
816 +
817 +static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc,
818 + const struct spi_mem_op *op)
819 +{
820 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
821 + u8 *data_buf = NULL, *data_buf_start, *oob_buf = NULL, *oob_buf_start;
822 + int ret, i;
823 + u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
824 +
825 + data_buf = op->data.buf.in;
826 + data_buf_start = data_buf;
827 +
828 + oob_buf = snandc->qspi->oob_buf;
829 + oob_buf_start = oob_buf;
830 +
831 + snandc->buf_count = 0;
832 + snandc->buf_start = 0;
833 + qcom_clear_read_regs(snandc);
834 +
835 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
836 + (num_cw - 1) << CW_PER_PAGE;
837 + cfg1 = ecc_cfg->cfg1;
838 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
839 +
840 + snandc->regs->addr0 = snandc->qspi->addr1;
841 + snandc->regs->addr1 = snandc->qspi->addr2;
842 + snandc->regs->cmd = snandc->qspi->cmd;
843 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
844 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
845 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
846 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
847 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
848 + snandc->regs->exec = cpu_to_le32(1);
849 +
850 + qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
851 +
852 + qcom_clear_bam_transaction(snandc);
853 +
854 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
855 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
856 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
857 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
858 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
859 + NAND_ERASED_CW_DETECT_CFG, 1,
860 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
861 +
862 + for (i = 0; i < num_cw; i++) {
863 + int data_size, oob_size;
864 +
865 + if (i == (num_cw - 1)) {
866 + data_size = 512 - ((num_cw - 1) << 2);
867 + oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
868 + ecc_cfg->spare_bytes;
869 + } else {
870 + data_size = ecc_cfg->cw_data;
871 + oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
872 + }
873 +
874 + if (data_buf && oob_buf) {
875 + qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0);
876 + qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1);
877 + } else if (data_buf) {
878 + qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1);
879 + } else {
880 + qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
881 + }
882 +
883 + qcom_spi_config_cw_read(snandc, true, i);
884 +
885 + if (data_buf)
886 + qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf,
887 + data_size, 0);
888 + if (oob_buf) {
889 + int j;
890 +
891 + for (j = 0; j < ecc_cfg->bbm_size; j++)
892 + *oob_buf++ = 0xff;
893 +
894 + qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
895 + oob_buf, oob_size, 0);
896 + }
897 +
898 + if (data_buf)
899 + data_buf += data_size;
900 + if (oob_buf)
901 + oob_buf += oob_size;
902 + }
903 +
904 + ret = qcom_submit_descs(snandc);
905 + if (ret) {
906 + dev_err(snandc->dev, "failure to read page\n");
907 + return ret;
908 + }
909 +
910 + return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start);
911 +}
912 +
913 +static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
914 + const struct spi_mem_op *op)
915 +{
916 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
917 + u8 *data_buf = NULL, *data_buf_start, *oob_buf = NULL, *oob_buf_start;
918 + int ret, i;
919 + u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
920 +
921 + oob_buf = op->data.buf.in;
922 + oob_buf_start = oob_buf;
923 +
924 + data_buf_start = data_buf;
925 +
926 + snandc->buf_count = 0;
927 + snandc->buf_start = 0;
928 + qcom_clear_read_regs(snandc);
929 + qcom_clear_bam_transaction(snandc);
930 +
931 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
932 + (num_cw - 1) << CW_PER_PAGE;
933 + cfg1 = ecc_cfg->cfg1;
934 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
935 +
936 + snandc->regs->addr0 = snandc->qspi->addr1;
937 + snandc->regs->addr1 = snandc->qspi->addr2;
938 + snandc->regs->cmd = snandc->qspi->cmd;
939 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
940 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
941 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
942 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
943 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
944 + snandc->regs->exec = cpu_to_le32(1);
945 +
946 + qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
947 +
948 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
949 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
950 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
951 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
952 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
953 + NAND_ERASED_CW_DETECT_CFG, 1,
954 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
955 +
956 + for (i = 0; i < num_cw; i++) {
957 + int data_size, oob_size;
958 +
959 + if (i == (num_cw - 1)) {
960 + data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
961 + oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
962 + ecc_cfg->spare_bytes;
963 + } else {
964 + data_size = ecc_cfg->cw_data;
965 + oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
966 + }
967 +
968 + qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
969 +
970 + qcom_spi_config_cw_read(snandc, true, i);
971 +
972 + if (oob_buf) {
973 + int j;
974 +
975 + for (j = 0; j < ecc_cfg->bbm_size; j++)
976 + *oob_buf++ = 0xff;
977 +
978 + qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
979 + oob_buf, oob_size, 0);
980 + }
981 +
982 + if (oob_buf)
983 + oob_buf += oob_size;
984 + }
985 +
986 + ret = qcom_submit_descs(snandc);
987 + if (ret) {
988 + dev_err(snandc->dev, "failure to read oob\n");
989 + return ret;
990 + }
991 +
992 + return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start);
993 +}
994 +
995 +static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
996 + const struct spi_mem_op *op)
997 +{
998 + if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
999 + return qcom_spi_read_page_raw(snandc, op);
1000 +
1001 + if (snandc->qspi->page_rw)
1002 + return qcom_spi_read_page_ecc(snandc, op);
1003 +
1004 + if (snandc->qspi->oob_rw && snandc->qspi->raw_rw)
1005 + return qcom_spi_read_last_cw(snandc, op);
1006 +
1007 + if (snandc->qspi->oob_rw)
1008 + return qcom_spi_read_page_oob(snandc, op);
1009 +
1010 + return 0;
1011 +}
1012 +
1013 +static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc)
1014 +{
1015 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
1016 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
1017 + qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG,
1018 + 1, NAND_BAM_NEXT_SGL);
1019 +}
1020 +
1021 +static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc)
1022 +{
1023 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1024 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1025 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1026 +
1027 + qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
1028 + qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
1029 + NAND_BAM_NEXT_SGL);
1030 +}
1031 +
1032 +static int qcom_spi_program_raw(struct qcom_nand_controller *snandc,
1033 + const struct spi_mem_op *op)
1034 +{
1035 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1036 + struct mtd_info *mtd = snandc->qspi->mtd;
1037 + u8 *data_buf = NULL, *oob_buf = NULL;
1038 + int i, ret;
1039 + int num_cw = snandc->qspi->num_cw;
1040 + u32 cfg0, cfg1, ecc_bch_cfg;
1041 +
1042 + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
1043 + (num_cw - 1) << CW_PER_PAGE;
1044 + cfg1 = ecc_cfg->cfg1_raw;
1045 + ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
1046 +
1047 + data_buf = snandc->qspi->data_buf;
1048 +
1049 + oob_buf = snandc->qspi->oob_buf;
1050 + memset(oob_buf, 0xff, OOB_BUF_SIZE);
1051 +
1052 + snandc->buf_count = 0;
1053 + snandc->buf_start = 0;
1054 + qcom_clear_read_regs(snandc);
1055 + qcom_clear_bam_transaction(snandc);
1056 +
1057 + snandc->regs->addr0 = snandc->qspi->addr1;
1058 + snandc->regs->addr1 = snandc->qspi->addr2;
1059 + snandc->regs->cmd = snandc->qspi->cmd;
1060 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1061 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1062 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1063 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
1064 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
1065 + snandc->regs->exec = cpu_to_le32(1);
1066 +
1067 + qcom_spi_config_page_write(snandc);
1068 +
1069 + for (i = 0; i < num_cw; i++) {
1070 + int data_size1, data_size2, oob_size1, oob_size2;
1071 + int reg_off = FLASH_BUF_ACC;
1072 +
1073 + data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
1074 + oob_size1 = ecc_cfg->bbm_size;
1075 +
1076 + if ((i == (num_cw - 1))) {
1077 + data_size2 = NANDC_STEP_SIZE - data_size1 -
1078 + ((num_cw - 1) << 2);
1079 + oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1080 + ecc_cfg->spare_bytes;
1081 + } else {
1082 + data_size2 = ecc_cfg->cw_data - data_size1;
1083 + oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
1084 + }
1085 +
1086 + qcom_write_data_dma(snandc, reg_off, data_buf, data_size1,
1087 + NAND_BAM_NO_EOT);
1088 + reg_off += data_size1;
1089 + data_buf += data_size1;
1090 +
1091 + qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1,
1092 + NAND_BAM_NO_EOT);
1093 + oob_buf += oob_size1;
1094 + reg_off += oob_size1;
1095 +
1096 + qcom_write_data_dma(snandc, reg_off, data_buf, data_size2,
1097 + NAND_BAM_NO_EOT);
1098 + reg_off += data_size2;
1099 + data_buf += data_size2;
1100 +
1101 + qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0);
1102 + oob_buf += oob_size2;
1103 +
1104 + qcom_spi_config_cw_write(snandc);
1105 + }
1106 +
1107 + ret = qcom_submit_descs(snandc);
1108 + if (ret) {
1109 + dev_err(snandc->dev, "failure to write raw page\n");
1110 + return ret;
1111 + }
1112 +
1113 + return 0;
1114 +}
1115 +
1116 +static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc,
1117 + const struct spi_mem_op *op)
1118 +{
1119 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1120 + u8 *data_buf = NULL, *oob_buf = NULL;
1121 + int i, ret;
1122 + int num_cw = snandc->qspi->num_cw;
1123 + u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1124 +
1125 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
1126 + (num_cw - 1) << CW_PER_PAGE;
1127 + cfg1 = ecc_cfg->cfg1;
1128 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1129 + ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1130 +
1131 + if (snandc->qspi->data_buf)
1132 + data_buf = snandc->qspi->data_buf;
1133 +
1134 + oob_buf = snandc->qspi->oob_buf;
1135 +
1136 + snandc->buf_count = 0;
1137 + snandc->buf_start = 0;
1138 + qcom_clear_read_regs(snandc);
1139 + qcom_clear_bam_transaction(snandc);
1140 +
1141 + snandc->regs->addr0 = snandc->qspi->addr1;
1142 + snandc->regs->addr1 = snandc->qspi->addr2;
1143 + snandc->regs->cmd = snandc->qspi->cmd;
1144 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1145 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1146 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1147 + snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1148 + snandc->regs->exec = cpu_to_le32(1);
1149 +
1150 + qcom_spi_config_page_write(snandc);
1151 +
1152 + for (i = 0; i < num_cw; i++) {
1153 + int data_size, oob_size;
1154 +
1155 + if (i == (num_cw - 1)) {
1156 + data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1157 + oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1158 + ecc_cfg->spare_bytes;
1159 + } else {
1160 + data_size = ecc_cfg->cw_data;
1161 + oob_size = ecc_cfg->bytes;
1162 + }
1163 +
1164 + if (data_buf)
1165 + qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size,
1166 + i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0);
1167 +
1168 + if (i == (num_cw - 1)) {
1169 + if (oob_buf) {
1170 + oob_buf += ecc_cfg->bbm_size;
1171 + qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size,
1172 + oob_buf, oob_size, 0);
1173 + }
1174 + }
1175 +
1176 + qcom_spi_config_cw_write(snandc);
1177 +
1178 + if (data_buf)
1179 + data_buf += data_size;
1180 + if (oob_buf)
1181 + oob_buf += oob_size;
1182 + }
1183 +
1184 + ret = qcom_submit_descs(snandc);
1185 + if (ret) {
1186 + dev_err(snandc->dev, "failure to write page\n");
1187 + return ret;
1188 + }
1189 +
1190 + return 0;
1191 +}
1192 +
1193 +static int qcom_spi_program_oob(struct qcom_nand_controller *snandc,
1194 + const struct spi_mem_op *op)
1195 +{
1196 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1197 + u8 *oob_buf = NULL;
1198 + int ret, col, data_size, oob_size;
1199 + int num_cw = snandc->qspi->num_cw;
1200 + u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1201 +
1202 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
1203 + (num_cw - 1) << CW_PER_PAGE;
1204 + cfg1 = ecc_cfg->cfg1;
1205 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1206 + ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1207 +
1208 + col = ecc_cfg->cw_size * (num_cw - 1);
1209 +
1210 + oob_buf = snandc->qspi->data_buf;
1211 +
1212 + snandc->buf_count = 0;
1213 + snandc->buf_start = 0;
1214 + qcom_clear_read_regs(snandc);
1215 + qcom_clear_bam_transaction(snandc);
1216 + snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
1217 + snandc->regs->addr1 = snandc->qspi->addr2;
1218 + snandc->regs->cmd = snandc->qspi->cmd;
1219 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1220 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1221 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1222 + snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1223 + snandc->regs->exec = cpu_to_le32(1);
1224 +
1225 + /* calculate the data and oob size for the last codeword/step */
1226 + data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1227 + oob_size = snandc->qspi->mtd->oobavail;
1228 +
1229 + memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data);
1230 + /* override new oob content to last codeword */
1231 + mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size,
1232 + oob_buf, 0, snandc->qspi->mtd->oobavail);
1233 + qcom_spi_config_page_write(snandc);
1234 + qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0);
1235 + qcom_spi_config_cw_write(snandc);
1236 +
1237 + ret = qcom_submit_descs(snandc);
1238 + if (ret) {
1239 + dev_err(snandc->dev, "failure to write oob\n");
1240 + return ret;
1241 + }
1242 +
1243 + return 0;
1244 +}
1245 +
1246 +static int qcom_spi_program_execute(struct qcom_nand_controller *snandc,
1247 + const struct spi_mem_op *op)
1248 +{
1249 + if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1250 + return qcom_spi_program_raw(snandc, op);
1251 +
1252 + if (snandc->qspi->page_rw)
1253 + return qcom_spi_program_ecc(snandc, op);
1254 +
1255 + if (snandc->qspi->oob_rw)
1256 + return qcom_spi_program_oob(snandc, op);
1257 +
1258 + return 0;
1259 +}
1260 +
1261 +static u32 qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode)
1262 +{
1263 + u32 cmd = 0x0;
1264 +
1265 + switch (opcode) {
1266 + case SPINAND_RESET:
1267 + cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
1268 + break;
1269 + case SPINAND_READID:
1270 + cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
1271 + break;
1272 + case SPINAND_GET_FEATURE:
1273 + cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
1274 + break;
1275 + case SPINAND_SET_FEATURE:
1276 + cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
1277 + QPIC_SET_FEATURE);
1278 + break;
1279 + case SPINAND_READ:
1280 + if (snandc->qspi->raw_rw) {
1281 + cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1282 + SPI_WP | SPI_HOLD | OP_PAGE_READ);
1283 + } else {
1284 + cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1285 + SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
1286 + }
1287 +
1288 + break;
1289 + case SPINAND_ERASE:
1290 + cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
1291 + SPI_HOLD | SPI_TRANSFER_MODE_x1;
1292 + break;
1293 + case SPINAND_WRITE_EN:
1294 + cmd = SPINAND_WRITE_EN;
1295 + break;
1296 + case SPINAND_PROGRAM_EXECUTE:
1297 + cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1298 + SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
1299 + break;
1300 + case SPINAND_PROGRAM_LOAD:
1301 + cmd = SPINAND_PROGRAM_LOAD;
1302 + break;
1303 + default:
1304 + dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
1305 + return -EOPNOTSUPP;
1306 + }
1307 +
1308 + return cmd;
1309 +}
1310 +
1311 +static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
1312 + const struct spi_mem_op *op)
1313 +{
1314 + struct qpic_snand_op s_op = {};
1315 + u32 cmd;
1316 +
1317 + cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
1318 + if (cmd < 0)
1319 + return cmd;
1320 +
1321 + s_op.cmd_reg = cmd;
1322 +
1323 + if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
1324 + snandc->qspi->data_buf = (u8 *)op->data.buf.out;
1325 +
1326 + return 0;
1327 +}
1328 +
1329 +static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
1330 + const struct spi_mem_op *op)
1331 +{
1332 + struct qpic_snand_op s_op = {};
1333 + u32 cmd;
1334 + int ret, opcode;
1335 +
1336 + cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
1337 + if (cmd < 0)
1338 + return cmd;
1339 +
1340 + s_op.cmd_reg = cmd;
1341 + s_op.addr1_reg = op->addr.val;
1342 + s_op.addr2_reg = 0;
1343 +
1344 + opcode = op->cmd.opcode;
1345 +
1346 + switch (opcode) {
1347 + case SPINAND_WRITE_EN:
1348 + return 0;
1349 + case SPINAND_PROGRAM_EXECUTE:
1350 + s_op.addr1_reg = op->addr.val << 16;
1351 + s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1352 + snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1353 + snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1354 + snandc->qspi->cmd = cpu_to_le32(cmd);
1355 + return qcom_spi_program_execute(snandc, op);
1356 + case SPINAND_READ:
1357 + s_op.addr1_reg = (op->addr.val << 16);
1358 + s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1359 + snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1360 + snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1361 + snandc->qspi->cmd = cpu_to_le32(cmd);
1362 + return 0;
1363 + case SPINAND_ERASE:
1364 + s_op.addr2_reg = (op->addr.val >> 16) & 0xffff;
1365 + s_op.addr1_reg = op->addr.val;
1366 + snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16);
1367 + snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1368 + snandc->qspi->cmd = cpu_to_le32(cmd);
1369 + qcom_spi_block_erase(snandc);
1370 + return 0;
1371 + default:
1372 + break;
1373 + }
1374 +
1375 + snandc->buf_count = 0;
1376 + snandc->buf_start = 0;
1377 + qcom_clear_read_regs(snandc);
1378 + qcom_clear_bam_transaction(snandc);
1379 +
1380 + snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg);
1381 + snandc->regs->exec = cpu_to_le32(1);
1382 + snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg);
1383 + snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg);
1384 +
1385 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1386 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1387 +
1388 + ret = qcom_submit_descs(snandc);
1389 + if (ret)
1390 + dev_err(snandc->dev, "failure in submitting cmd descriptor\n");
1391 +
1392 + return ret;
1393 +}
1394 +
1395 +static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op)
1396 +{
1397 + int ret, val, opcode;
1398 + bool copy = false, copy_ftr = false;
1399 +
1400 + ret = qcom_spi_send_cmdaddr(snandc, op);
1401 + if (ret)
1402 + return ret;
1403 +
1404 + snandc->buf_count = 0;
1405 + snandc->buf_start = 0;
1406 + qcom_clear_read_regs(snandc);
1407 + qcom_clear_bam_transaction(snandc);
1408 + opcode = op->cmd.opcode;
1409 +
1410 + switch (opcode) {
1411 + case SPINAND_READID:
1412 + snandc->buf_count = 4;
1413 + qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1414 + copy = true;
1415 + break;
1416 + case SPINAND_GET_FEATURE:
1417 + snandc->buf_count = 4;
1418 + qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1419 + copy_ftr = true;
1420 + break;
1421 + case SPINAND_SET_FEATURE:
1422 + snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out);
1423 + qcom_write_reg_dma(snandc, &snandc->regs->flash_feature,
1424 + NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1425 + break;
1426 + case SPINAND_PROGRAM_EXECUTE:
1427 + case SPINAND_WRITE_EN:
1428 + case SPINAND_RESET:
1429 + case SPINAND_ERASE:
1430 + case SPINAND_READ:
1431 + return 0;
1432 + default:
1433 + return -EOPNOTSUPP;
1434 + }
1435 +
1436 + ret = qcom_submit_descs(snandc);
1437 + if (ret)
1438 + dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode);
1439 +
1440 + if (copy) {
1441 + qcom_nandc_dev_to_mem(snandc, true);
1442 + memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
1443 + }
1444 +
1445 + if (copy_ftr) {
1446 + qcom_nandc_dev_to_mem(snandc, true);
1447 + val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf);
1448 + val >>= 8;
1449 + memcpy(op->data.buf.in, &val, snandc->buf_count);
1450 + }
1451 +
1452 + return ret;
1453 +}
1454 +
1455 +static bool qcom_spi_is_page_op(const struct spi_mem_op *op)
1456 +{
1457 + if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4)
1458 + return false;
1459 +
1460 + if (op->data.dir == SPI_MEM_DATA_IN) {
1461 + if (op->addr.buswidth == 4 && op->data.buswidth == 4)
1462 + return true;
1463 +
1464 + if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1465 + return true;
1466 +
1467 + } else if (op->data.dir == SPI_MEM_DATA_OUT) {
1468 + if (op->data.buswidth == 4)
1469 + return true;
1470 + if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1471 + return true;
1472 + }
1473 +
1474 + return false;
1475 +}
1476 +
1477 +static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
1478 +{
1479 + if (!spi_mem_default_supports_op(mem, op))
1480 + return false;
1481 +
1482 + if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
1483 + return false;
1484 +
1485 + if (qcom_spi_is_page_op(op))
1486 + return true;
1487 +
1488 + return ((!op->addr.nbytes || op->addr.buswidth == 1) &&
1489 + (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
1490 + (!op->data.nbytes || op->data.buswidth == 1));
1491 +}
1492 +
1493 +static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
1494 +{
1495 + struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller);
1496 +
1497 + dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
1498 + op->addr.val, op->addr.buswidth, op->addr.nbytes,
1499 + op->data.buswidth, op->data.nbytes);
1500 +
1501 + if (qcom_spi_is_page_op(op)) {
1502 + if (op->data.dir == SPI_MEM_DATA_IN)
1503 + return qcom_spi_read_page(snandc, op);
1504 + if (op->data.dir == SPI_MEM_DATA_OUT)
1505 + return qcom_spi_write_page(snandc, op);
1506 + } else {
1507 + return qcom_spi_io_op(snandc, op);
1508 + }
1509 +
1510 + return 0;
1511 +}
1512 +
1513 +static const struct spi_controller_mem_ops qcom_spi_mem_ops = {
1514 + .supports_op = qcom_spi_supports_op,
1515 + .exec_op = qcom_spi_exec_op,
1516 +};
1517 +
1518 +static const struct spi_controller_mem_caps qcom_spi_mem_caps = {
1519 + .ecc = true,
1520 +};
1521 +
1522 +static int qcom_spi_probe(struct platform_device *pdev)
1523 +{
1524 + struct device *dev = &pdev->dev;
1525 + struct spi_controller *ctlr;
1526 + struct qcom_nand_controller *snandc;
1527 + struct qpic_spi_nand *qspi;
1528 + struct qpic_ecc *ecc;
1529 + struct resource *res;
1530 + const void *dev_data;
1531 + int ret;
1532 +
1533 + ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
1534 + if (!ecc)
1535 + return -ENOMEM;
1536 +
1537 + qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
1538 + if (!qspi)
1539 + return -ENOMEM;
1540 +
1541 + ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false);
1542 + if (!ctlr)
1543 + return -ENOMEM;
1544 +
1545 + platform_set_drvdata(pdev, ctlr);
1546 +
1547 + snandc = spi_controller_get_devdata(ctlr);
1548 + qspi->snandc = snandc;
1549 +
1550 + snandc->dev = dev;
1551 + snandc->qspi = qspi;
1552 + snandc->qspi->ctlr = ctlr;
1553 + snandc->qspi->ecc = ecc;
1554 +
1555 + dev_data = of_device_get_match_data(dev);
1556 + if (!dev_data) {
1557 + dev_err(&pdev->dev, "failed to get device data\n");
1558 + return -ENODEV;
1559 + }
1560 +
1561 + snandc->props = dev_data;
1562 + snandc->dev = &pdev->dev;
1563 +
1564 + snandc->core_clk = devm_clk_get(dev, "core");
1565 + if (IS_ERR(snandc->core_clk))
1566 + return PTR_ERR(snandc->core_clk);
1567 +
1568 + snandc->aon_clk = devm_clk_get(dev, "aon");
1569 + if (IS_ERR(snandc->aon_clk))
1570 + return PTR_ERR(snandc->aon_clk);
1571 +
1572 + snandc->qspi->iomacro_clk = devm_clk_get(dev, "iom");
1573 + if (IS_ERR(snandc->qspi->iomacro_clk))
1574 + return PTR_ERR(snandc->qspi->iomacro_clk);
1575 +
1576 + snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1577 + if (IS_ERR(snandc->base))
1578 + return PTR_ERR(snandc->base);
1579 +
1580 + snandc->base_phys = res->start;
1581 + snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res),
1582 + DMA_BIDIRECTIONAL, 0);
1583 + if (dma_mapping_error(dev, snandc->base_dma))
1584 + return -ENXIO;
1585 +
1586 + ret = clk_prepare_enable(snandc->core_clk);
1587 + if (ret)
1588 + goto err_dis_core_clk;
1589 +
1590 + ret = clk_prepare_enable(snandc->aon_clk);
1591 + if (ret)
1592 + goto err_dis_aon_clk;
1593 +
1594 + ret = clk_prepare_enable(snandc->qspi->iomacro_clk);
1595 + if (ret)
1596 + goto err_dis_iom_clk;
1597 +
1598 + ret = qcom_nandc_alloc(snandc);
1599 + if (ret)
1600 + goto err_snand_alloc;
1601 +
1602 + ret = qcom_spi_init(snandc);
1603 + if (ret)
1604 + goto err_spi_init;
1605 +
1606 + /* setup ECC engine */
1607 + snandc->qspi->ecc_eng.dev = &pdev->dev;
1608 + snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
1609 + snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined;
1610 + snandc->qspi->ecc_eng.priv = snandc;
1611 +
1612 + ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng);
1613 + if (ret) {
1614 + dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret);
1615 + goto err_spi_init;
1616 + }
1617 +
1618 + ctlr->num_chipselect = QPIC_QSPI_NUM_CS;
1619 + ctlr->mem_ops = &qcom_spi_mem_ops;
1620 + ctlr->mem_caps = &qcom_spi_mem_caps;
1621 + ctlr->dev.of_node = pdev->dev.of_node;
1622 + ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL |
1623 + SPI_TX_QUAD | SPI_RX_QUAD;
1624 +
1625 + ret = spi_register_controller(ctlr);
1626 + if (ret) {
1627 + dev_err(&pdev->dev, "spi_register_controller failed.\n");
1628 + goto err_spi_init;
1629 + }
1630 +
1631 + return 0;
1632 +
1633 +err_spi_init:
1634 + qcom_nandc_unalloc(snandc);
1635 +err_snand_alloc:
1636 + clk_disable_unprepare(snandc->qspi->iomacro_clk);
1637 +err_dis_iom_clk:
1638 + clk_disable_unprepare(snandc->aon_clk);
1639 +err_dis_aon_clk:
1640 + clk_disable_unprepare(snandc->core_clk);
1641 +err_dis_core_clk:
1642 + dma_unmap_resource(dev, res->start, resource_size(res),
1643 + DMA_BIDIRECTIONAL, 0);
1644 + return ret;
1645 +}
1646 +
1647 +static void qcom_spi_remove(struct platform_device *pdev)
1648 +{
1649 + struct spi_controller *ctlr = platform_get_drvdata(pdev);
1650 + struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr);
1651 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1652 +
1653 + spi_unregister_controller(ctlr);
1654 +
1655 + qcom_nandc_unalloc(snandc);
1656 +
1657 + clk_disable_unprepare(snandc->aon_clk);
1658 + clk_disable_unprepare(snandc->core_clk);
1659 + clk_disable_unprepare(snandc->qspi->iomacro_clk);
1660 +
1661 + dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res),
1662 + DMA_BIDIRECTIONAL, 0);
1663 +}
1664 +
1665 +static const struct qcom_nandc_props ipq9574_snandc_props = {
1666 + .dev_cmd_reg_start = 0x7000,
1667 + .supports_bam = true,
1668 +};
1669 +
1670 +static const struct of_device_id qcom_snandc_of_match[] = {
1671 + {
1672 + .compatible = "qcom,spi-qpic-snand",
1673 + .data = &ipq9574_snandc_props,
1674 + },
1675 + {}
1676 +}
1677 +MODULE_DEVICE_TABLE(of, qcom_snandc_of_match);
1678 +
1679 +static struct platform_driver qcom_spi_driver = {
1680 + .driver = {
1681 + .name = "qcom_snand",
1682 + .of_match_table = qcom_snandc_of_match,
1683 + },
1684 + .probe = qcom_spi_probe,
1685 + .remove = qcom_spi_remove,
1686 +};
1687 +module_platform_driver(qcom_spi_driver);
1688 +
1689 +MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores");
1690 +MODULE_AUTHOR("Md Sadre Alam <quic_mdalam@quicinc.com>");
1691 +MODULE_LICENSE("GPL");
1692 +
1693 --- a/include/linux/mtd/nand-qpic-common.h
1694 +++ b/include/linux/mtd/nand-qpic-common.h
1695 @@ -322,6 +322,10 @@ struct nandc_regs {
1696 __le32 read_location_last1;
1697 __le32 read_location_last2;
1698 __le32 read_location_last3;
1699 + __le32 spi_cfg;
1700 + __le32 num_addr_cycle;
1701 + __le32 busy_wait_cnt;
1702 + __le32 flash_feature;
1703
1704 __le32 erased_cw_detect_cfg_clr;
1705 __le32 erased_cw_detect_cfg_set;
1706 @@ -336,6 +340,7 @@ struct nandc_regs {
1707 *
1708 * @core_clk: controller clock
1709 * @aon_clk: another controller clock
1710 + * @iomacro_clk: io macro clock
1711 *
1712 * @regs: a contiguous chunk of memory for DMA register
1713 * writes. contains the register values to be
1714 @@ -345,6 +350,7 @@ struct nandc_regs {
1715 * initialized via DT match data
1716 *
1717 * @controller: base controller structure
1718 + * @qspi: qpic spi structure
1719 * @host_list: list containing all the chips attached to the
1720 * controller
1721 *
1722 @@ -389,6 +395,7 @@ struct qcom_nand_controller {
1723 const struct qcom_nandc_props *props;
1724
1725 struct nand_controller *controller;
1726 + struct qpic_spi_nand *qspi;
1727 struct list_head host_list;
1728
1729 union {
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