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1 From 6ab3d50b106c9aea123a80551a6c9deace83b914 Mon Sep 17 00:00:00 2001
2 From: Qiang Yu <quic_qianyu@quicinc.com>
3 Date: Tue, 7 Nov 2023 16:14:49 +0800
4 Subject: [PATCH] bus: mhi: host: Add a separate timeout parameter for waiting
5 ready
6
7 Some devices(eg. SDX75) take longer than expected (default, 8 seconds) to
8 set ready after reboot. Hence add optional ready timeout parameter and pass
9 the appropriate timeout value to mhi_poll_reg_field() to wait enough for
10 device ready as part of power up sequence.
11
12 Signed-off-by: Qiang Yu <quic_qianyu@quicinc.com>
13 Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
14 Link: https://lore.kernel.org/r/1699344890-87076-2-git-send-email-quic_qianyu@quicinc.com
15 Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
16 ---
17 drivers/bus/mhi/host/init.c | 1 +
18 drivers/bus/mhi/host/internal.h | 2 +-
19 drivers/bus/mhi/host/main.c | 5 +++--
20 drivers/bus/mhi/host/pm.c | 24 +++++++++++++++++-------
21 include/linux/mhi.h | 4 ++++
22 5 files changed, 26 insertions(+), 10 deletions(-)
23
24 --- a/drivers/bus/mhi/host/init.c
25 +++ b/drivers/bus/mhi/host/init.c
26 @@ -882,6 +882,7 @@ static int parse_config(struct mhi_contr
27 if (!mhi_cntrl->timeout_ms)
28 mhi_cntrl->timeout_ms = MHI_TIMEOUT_MS;
29
30 + mhi_cntrl->ready_timeout_ms = config->ready_timeout_ms;
31 mhi_cntrl->bounce_buf = config->use_bounce_buf;
32 mhi_cntrl->buffer_len = config->buf_len;
33 if (!mhi_cntrl->buffer_len)
34 --- a/drivers/bus/mhi/host/internal.h
35 +++ b/drivers/bus/mhi/host/internal.h
36 @@ -324,7 +324,7 @@ int __must_check mhi_read_reg_field(stru
37 u32 *out);
38 int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl,
39 void __iomem *base, u32 offset, u32 mask,
40 - u32 val, u32 delayus);
41 + u32 val, u32 delayus, u32 timeout_ms);
42 void mhi_write_reg(struct mhi_controller *mhi_cntrl, void __iomem *base,
43 u32 offset, u32 val);
44 int __must_check mhi_write_reg_field(struct mhi_controller *mhi_cntrl,
45 --- a/drivers/bus/mhi/host/main.c
46 +++ b/drivers/bus/mhi/host/main.c
47 @@ -40,10 +40,11 @@ int __must_check mhi_read_reg_field(stru
48
49 int __must_check mhi_poll_reg_field(struct mhi_controller *mhi_cntrl,
50 void __iomem *base, u32 offset,
51 - u32 mask, u32 val, u32 delayus)
52 + u32 mask, u32 val, u32 delayus,
53 + u32 timeout_ms)
54 {
55 int ret;
56 - u32 out, retry = (mhi_cntrl->timeout_ms * 1000) / delayus;
57 + u32 out, retry = (timeout_ms * 1000) / delayus;
58
59 while (retry--) {
60 ret = mhi_read_reg_field(mhi_cntrl, base, offset, mask, &out);
61 --- a/drivers/bus/mhi/host/pm.c
62 +++ b/drivers/bus/mhi/host/pm.c
63 @@ -171,6 +171,7 @@ int mhi_ready_state_transition(struct mh
64 enum mhi_pm_state cur_state;
65 struct device *dev = &mhi_cntrl->mhi_dev->dev;
66 u32 interval_us = 25000; /* poll register field every 25 milliseconds */
67 + u32 timeout_ms;
68 int ret, i;
69
70 /* Check if device entered error state */
71 @@ -181,14 +182,18 @@ int mhi_ready_state_transition(struct mh
72
73 /* Wait for RESET to be cleared and READY bit to be set by the device */
74 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
75 - MHICTRL_RESET_MASK, 0, interval_us);
76 + MHICTRL_RESET_MASK, 0, interval_us,
77 + mhi_cntrl->timeout_ms);
78 if (ret) {
79 dev_err(dev, "Device failed to clear MHI Reset\n");
80 return ret;
81 }
82
83 + timeout_ms = mhi_cntrl->ready_timeout_ms ?
84 + mhi_cntrl->ready_timeout_ms : mhi_cntrl->timeout_ms;
85 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHISTATUS,
86 - MHISTATUS_READY_MASK, 1, interval_us);
87 + MHISTATUS_READY_MASK, 1, interval_us,
88 + timeout_ms);
89 if (ret) {
90 dev_err(dev, "Device failed to enter MHI Ready\n");
91 return ret;
92 @@ -487,7 +492,7 @@ static void mhi_pm_disable_transition(st
93
94 /* Wait for the reset bit to be cleared by the device */
95 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
96 - MHICTRL_RESET_MASK, 0, 25000);
97 + MHICTRL_RESET_MASK, 0, 25000, mhi_cntrl->timeout_ms);
98 if (ret)
99 dev_err(dev, "Device failed to clear MHI Reset\n");
100
101 @@ -500,8 +505,8 @@ static void mhi_pm_disable_transition(st
102 if (!MHI_IN_PBL(mhi_get_exec_env(mhi_cntrl))) {
103 /* wait for ready to be set */
104 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs,
105 - MHISTATUS,
106 - MHISTATUS_READY_MASK, 1, 25000);
107 + MHISTATUS, MHISTATUS_READY_MASK,
108 + 1, 25000, mhi_cntrl->timeout_ms);
109 if (ret)
110 dev_err(dev, "Device failed to enter READY state\n");
111 }
112 @@ -1125,7 +1130,8 @@ int mhi_async_power_up(struct mhi_contro
113 if (state == MHI_STATE_SYS_ERR) {
114 mhi_set_mhi_state(mhi_cntrl, MHI_STATE_RESET);
115 ret = mhi_poll_reg_field(mhi_cntrl, mhi_cntrl->regs, MHICTRL,
116 - MHICTRL_RESET_MASK, 0, interval_us);
117 + MHICTRL_RESET_MASK, 0, interval_us,
118 + mhi_cntrl->timeout_ms);
119 if (ret) {
120 dev_info(dev, "Failed to reset MHI due to syserr state\n");
121 goto error_exit;
122 @@ -1216,14 +1222,18 @@ EXPORT_SYMBOL_GPL(mhi_power_down);
123 int mhi_sync_power_up(struct mhi_controller *mhi_cntrl)
124 {
125 int ret = mhi_async_power_up(mhi_cntrl);
126 + u32 timeout_ms;
127
128 if (ret)
129 return ret;
130
131 + /* Some devices need more time to set ready during power up */
132 + timeout_ms = mhi_cntrl->ready_timeout_ms ?
133 + mhi_cntrl->ready_timeout_ms : mhi_cntrl->timeout_ms;
134 wait_event_timeout(mhi_cntrl->state_event,
135 MHI_IN_MISSION_MODE(mhi_cntrl->ee) ||
136 MHI_PM_IN_ERROR_STATE(mhi_cntrl->pm_state),
137 - msecs_to_jiffies(mhi_cntrl->timeout_ms));
138 + msecs_to_jiffies(timeout_ms));
139
140 ret = (MHI_IN_MISSION_MODE(mhi_cntrl->ee)) ? 0 : -ETIMEDOUT;
141 if (ret)
142 --- a/include/linux/mhi.h
143 +++ b/include/linux/mhi.h
144 @@ -266,6 +266,7 @@ struct mhi_event_config {
145 * struct mhi_controller_config - Root MHI controller configuration
146 * @max_channels: Maximum number of channels supported
147 * @timeout_ms: Timeout value for operations. 0 means use default
148 + * @ready_timeout_ms: Timeout value for waiting device to be ready (optional)
149 * @buf_len: Size of automatically allocated buffers. 0 means use default
150 * @num_channels: Number of channels defined in @ch_cfg
151 * @ch_cfg: Array of defined channels
152 @@ -277,6 +278,7 @@ struct mhi_event_config {
153 struct mhi_controller_config {
154 u32 max_channels;
155 u32 timeout_ms;
156 + u32 ready_timeout_ms;
157 u32 buf_len;
158 u32 num_channels;
159 const struct mhi_channel_config *ch_cfg;
160 @@ -330,6 +332,7 @@ struct mhi_controller_config {
161 * @pm_mutex: Mutex for suspend/resume operation
162 * @pm_lock: Lock for protecting MHI power management state
163 * @timeout_ms: Timeout in ms for state transitions
164 + * @ready_timeout_ms: Timeout in ms for waiting device to be ready (optional)
165 * @pm_state: MHI power management state
166 * @db_access: DB access states
167 * @ee: MHI device execution environment
168 @@ -419,6 +422,7 @@ struct mhi_controller {
169 struct mutex pm_mutex;
170 rwlock_t pm_lock;
171 u32 timeout_ms;
172 + u32 ready_timeout_ms;
173 u32 pm_state;
174 u32 db_access;
175 enum mhi_ee_type ee;
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