1 From f55f26750fa582a9ab9eddc0980b0633bb42d75b Mon Sep 17 00:00:00 2001
2 From: Boris Brezillon <boris.brezillon@bootlin.com>
3 Date: Fri, 3 Aug 2018 11:22:31 +0200
4 Subject: [PATCH 761/773] drm/vc4: Fix X/Y positioning of planes using T_TILES
7 X/Y positioning of T-format buffers is quite tricky and the current
8 implementation was failing to position a plane using this format
9 correctly when the CRTC X, Y or both X and Y offsets were negative.
10 It was also failing when the SRC X/Y offsets were != 0.
12 Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
13 Reviewed-by: Eric Anholt <eric@anholt.net>
14 Link: https://patchwork.freedesktop.org/patch/msgid/20180803092231.26446-5-boris.brezillon@bootlin.com
16 drivers/gpu/drm/vc4/vc4_plane.c | 50 ++++++++++++++++++++++++++++-----
17 1 file changed, 43 insertions(+), 7 deletions(-)
19 --- a/drivers/gpu/drm/vc4/vc4_plane.c
20 +++ b/drivers/gpu/drm/vc4/vc4_plane.c
21 @@ -578,22 +578,58 @@ static int vc4_plane_mode_set(struct drm
22 (i ? h_subsample : 1) *
28 case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
29 - /* For T-tiled, the FB pitch is "how many bytes from
30 - * one row to the next, such that pitch * tile_h ==
31 - * tile_size * tiles_per_row."
33 u32 tile_size_shift = 12; /* T tiles are 4kb */
34 + /* Whole-tile offsets, mostly for setting the pitch. */
35 + u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
36 u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
37 + u32 tile_w_mask = (1 << tile_w_shift) - 1;
38 + /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
39 + * the height (in pixels) of a 4k tile.
41 + u32 tile_h_mask = (2 << tile_h_shift) - 1;
42 + /* For T-tiled, the FB pitch is "how many bytes from one row to
43 + * the next, such that
45 + * pitch * tile_h == tile_size * tiles_per_row
47 u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
48 + u32 tiles_l = vc4_state->src_x >> tile_w_shift;
49 + u32 tiles_r = tiles_w - tiles_l;
50 + u32 tiles_t = vc4_state->src_y >> tile_h_shift;
51 + /* Intra-tile offsets, which modify the base address (the
52 + * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
55 + u32 tile_y = (vc4_state->src_y >> 4) & 1;
56 + u32 subtile_y = (vc4_state->src_y >> 2) & 3;
57 + u32 utile_y = vc4_state->src_y & 3;
58 + u32 x_off = vc4_state->src_x & tile_w_mask;
59 + u32 y_off = vc4_state->src_y & tile_h_mask;
61 tiling = SCALER_CTL0_TILING_256B_OR_T;
62 + pitch0 = (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
63 + VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
64 + VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
65 + VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
66 + vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
67 + vc4_state->offsets[0] += subtile_y << 8;
68 + vc4_state->offsets[0] += utile_y << 4;
70 + /* Rows of tiles alternate left-to-right and right-to-left. */
72 + pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
73 + vc4_state->offsets[0] += (tiles_w - tiles_l) <<
75 + vc4_state->offsets[0] -= (1 + !tile_y) << 10;
77 + vc4_state->offsets[0] += tiles_l << tile_size_shift;
78 + vc4_state->offsets[0] += tile_y << 10;
81 - pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) |
82 - VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) |
83 - VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R));