git.openwrt.org Git - openwrt/staging/ansuel.git/blob

   1 From 94b0f301f6ee92f79a2fe2c655dfdbdfe2aec536 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
   3 Date: Sun, 19 Nov 2023 22:24:16 +0100
   4 Subject: [PATCH] dt-bindings: arm: mediatek: move ethsys controller & convert
   5  to DT schema
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 DT schema helps validating DTS files. Binding was moved to clock/ as
  11 this hardware is a clock provider. Example required a small fix for
  12 "reg" value (1 address cell + 1 size cell).
  13
  14 Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
  15 Reviewed-by: Rob Herring <robh@kernel.org>
  16 Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com
  17 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  18 ---
  19  .../bindings/arm/mediatek/mediatek,ethsys.txt | 29 ----------
  20  .../bindings/clock/mediatek,ethsys.yaml       | 54 +++++++++++++++++++
  21  2 files changed, 54 insertions(+), 29 deletions(-)
  22  delete mode 100644 Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
  23  create mode 100644 Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
  24
  25 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,ethsys.txt
  26 +++ /dev/null
  27 @@ -1,29 +0,0 @@
  28 -Mediatek ethsys controller
  29 -============================
  30 -
  31 -The Mediatek ethsys controller provides various clocks to the system.
  32 -
  33 -Required Properties:
  34 -
  35 -- compatible: Should be:
  36 -       - "mediatek,mt2701-ethsys", "syscon"
  37 -       - "mediatek,mt7622-ethsys", "syscon"
  38 -       - "mediatek,mt7623-ethsys", "mediatek,mt2701-ethsys", "syscon"
  39 -       - "mediatek,mt7629-ethsys", "syscon"
  40 -       - "mediatek,mt7981-ethsys", "syscon"
  41 -       - "mediatek,mt7986-ethsys", "syscon"
  42 -- #clock-cells: Must be 1
  43 -- #reset-cells: Must be 1
  44 -
  45 -The ethsys controller uses the common clk binding from
  46 -Documentation/devicetree/bindings/clock/clock-bindings.txt
  47 -The available clocks are defined in dt-bindings/clock/mt*-clk.h.
  48 -
  49 -Example:
  50 -
  51 -ethsys: clock-controller@1b000000 {
  52 -       compatible = "mediatek,mt2701-ethsys", "syscon";
  53 -       reg = <0 0x1b000000 0 0x1000>;
  54 -       #clock-cells = <1>;
  55 -       #reset-cells = <1>;
  56 -};
  57 --- /dev/null
  58 +++ b/Documentation/devicetree/bindings/clock/mediatek,ethsys.yaml
  59 @@ -0,0 +1,54 @@
  60 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  61 +%YAML 1.2
  62 +---
  63 +$id: http://devicetree.org/schemas/clock/mediatek,ethsys.yaml#
  64 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  65 +
  66 +title: Mediatek ethsys controller
  67 +
  68 +description:
  69 +  The available clocks are defined in dt-bindings/clock/mt*-clk.h.
  70 +
  71 +maintainers:
  72 +  - James Liao <jamesjj.liao@mediatek.com>
  73 +
  74 +properties:
  75 +  compatible:
  76 +    oneOf:
  77 +      - items:
  78 +          - enum:
  79 +              - mediatek,mt2701-ethsys
  80 +              - mediatek,mt7622-ethsys
  81 +              - mediatek,mt7629-ethsys
  82 +              - mediatek,mt7981-ethsys
  83 +              - mediatek,mt7986-ethsys
  84 +          - const: syscon
  85 +      - items:
  86 +          - const: mediatek,mt7623-ethsys
  87 +          - const: mediatek,mt2701-ethsys
  88 +          - const: syscon
  89 +
  90 +  reg:
  91 +    maxItems: 1
  92 +
  93 +  "#clock-cells":
  94 +    const: 1
  95 +
  96 +  "#reset-cells":
  97 +    const: 1
  98 +
  99 +required:
 100 +  - reg
 101 +  - "#clock-cells"
 102 +  - "#reset-cells"
 103 +
 104 +additionalProperties: false
 105 +
 106 +examples:
 107 +  - |
 108 +    clock-controller@1b000000 {
 109 +        compatible = "mediatek,mt2701-ethsys", "syscon";
 110 +        reg = <0x1b000000 0x1000>;
 111 +        #clock-cells = <1>;
 112 +        #reset-cells = <1>;
 113 +    };