1 From e03cea60c3db8c6b011cc36ecef9281dff8377f3 Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Wed, 25 Jan 2023 21:35:16 +0100
4 Subject: [PATCH] net: dsa: qca8k: add QCA8K_ATU_TABLE_SIZE define for fdb
7 Add and use QCA8K_ATU_TABLE_SIZE instead of hardcoding the ATU size with
8 a pure number and using sizeof on the array.
10 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
11 Signed-off-by: David S. Miller <davem@davemloft.net>
13 drivers/net/dsa/qca/qca8k-common.c | 10 ++++++----
14 drivers/net/dsa/qca/qca8k.h | 2 ++
15 2 files changed, 8 insertions(+), 4 deletions(-)
17 --- a/drivers/net/dsa/qca/qca8k-common.c
18 +++ b/drivers/net/dsa/qca/qca8k-common.c
19 @@ -150,11 +150,12 @@ static int qca8k_busy_wait(struct qca8k_
21 static int qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
24 + u32 reg[QCA8K_ATU_TABLE_SIZE];
27 /* load the ARL table into an array */
28 - ret = qca8k_bulk_read(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg));
29 + ret = qca8k_bulk_read(priv, QCA8K_REG_ATU_DATA0, reg,
30 + QCA8K_ATU_TABLE_SIZE * sizeof(u32));
34 @@ -178,7 +179,7 @@ static int qca8k_fdb_read(struct qca8k_p
35 static void qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask,
36 const u8 *mac, u8 aging)
39 + u32 reg[QCA8K_ATU_TABLE_SIZE] = { 0 };
42 reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);
43 @@ -195,7 +196,8 @@ static void qca8k_fdb_write(struct qca8k
44 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);
46 /* load the array into the ARL table */
47 - qca8k_bulk_write(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg));
48 + qca8k_bulk_write(priv, QCA8K_REG_ATU_DATA0, reg,
49 + QCA8K_ATU_TABLE_SIZE * sizeof(u32));
52 static int qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd,
53 --- a/drivers/net/dsa/qca/qca8k.h
54 +++ b/drivers/net/dsa/qca/qca8k.h
56 #define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
58 /* Lookup registers */
59 +#define QCA8K_ATU_TABLE_SIZE 3 /* 12 bytes wide table / sizeof(u32) */
61 #define QCA8K_REG_ATU_DATA0 0x600
62 #define QCA8K_ATU_ADDR2_MASK GENMASK(31, 24)
63 #define QCA8K_ATU_ADDR3_MASK GENMASK(23, 16)