git.openwrt.org Git - openwrt/staging/jogo.git/blob

   1 From de3c4bf648975ea0b1d344d811e9b0748907b47c Mon Sep 17 00:00:00 2001
   2 From: Ansuel Smith <ansuelsmth@gmail.com>
   3 Date: Mon, 15 Jun 2020 23:06:04 +0200
   4 Subject: PCI: qcom: Add support for tx term offset for rev 2.1.0
   5
   6 Add tx term offset support to pcie qcom driver need in some revision of
   7 the ipq806x SoC. Ipq8064 needs tx term offset set to 7.
   8
   9 Link: https://lore.kernel.org/r/20200615210608.21469-9-ansuelsmth@gmail.com
  10 Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver")
  11 Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
  12 Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
  13 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  14 Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
  15 Cc: stable@vger.kernel.org # v4.5+
  16 ---
  17  drivers/pci/controller/dwc/pcie-qcom.c | 17 ++++++++++++++++-
  18  1 file changed, 16 insertions(+), 1 deletion(-)
  19
  20 --- a/drivers/pci/controller/dwc/pcie-qcom.c
  21 +++ b/drivers/pci/controller/dwc/pcie-qcom.c
  22 @@ -45,7 +45,13 @@
  23  #define PCIE_CAP_CPL_TIMEOUT_DISABLE           0x10
  24
  25  #define PCIE20_PARF_PHY_CTRL                   0x40
  26 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK      GENMASK(20, 16)
  27 +#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)                ((x) << 16)
  28 +
  29  #define PCIE20_PARF_PHY_REFCLK                 0x4C
  30 +#define PHY_REFCLK_SSP_EN                      BIT(16)
  31 +#define PHY_REFCLK_USE_PAD                     BIT(12)
  32 +
  33  #define PCIE20_PARF_DBI_BASE_ADDR              0x168
  34  #define PCIE20_PARF_SLV_ADDR_SPACE_SIZE                0x16C
  35  #define PCIE20_PARF_MHI_CLOCK_RESET_CTRL       0x174
  36 @@ -360,9 +366,18 @@ static int qcom_pcie_init_2_1_0(struct q
  37                 writel(PHY_RX0_EQ(4), pcie->parf + PCIE20_PARF_CONFIG_BITS);
  38         }
  39
  40 +       if (of_device_is_compatible(node, "qcom,pcie-ipq8064")) {
  41 +               /* set TX termination offset */
  42 +               val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
  43 +               val &= ~PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK;
  44 +               val |= PHY_CTRL_PHY_TX0_TERM_OFFSET(7);
  45 +               writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL);
  46 +       }
  47 +
  48         /* enable external reference clock */
  49         val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK);
  50 -       val |= BIT(16);
  51 +       val &= ~PHY_REFCLK_USE_PAD;
  52 +       val |= PHY_REFCLK_SSP_EN;
  53         writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK);
  54
  55         /* wait for clock acquisition */