git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From 076dcedc6628c6bf92bd17bfcf8fb7b1af62bfb6 Mon Sep 17 00:00:00 2001
   2 From: William Zhang <william.zhang@broadcom.com>
   3 Date: Wed, 1 Jun 2022 15:56:51 -0700
   4 Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM63158
   5
   6 Add DTS for ARMv8 based broadband SoC BCM63158. bcm63158.dtsi is the
   7 SoC description DTS header and bcm963158.dts is a simple DTS file for
   8 Broadcom BCM963158 Reference board that only enable the UART port.
   9
  10 Signed-off-by: William Zhang <william.zhang@broadcom.com>
  11 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  12 ---
  13  arch/arm64/boot/dts/broadcom/Makefile         |   1 +
  14  arch/arm64/boot/dts/broadcom/bcmbca/Makefile  |   2 +
  15  .../boot/dts/broadcom/bcmbca/bcm63158.dtsi    | 128 ++++++++++++++++++
  16  .../boot/dts/broadcom/bcmbca/bcm963158.dts    |  30 ++++
  17  4 files changed, 161 insertions(+)
  18  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  19  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
  20  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
  21
  22 --- a/arch/arm64/boot/dts/broadcom/Makefile
  23 +++ b/arch/arm64/boot/dts/broadcom/Makefile
  24 @@ -7,5 +7,6 @@ dtb-$(CONFIG_ARCH_BCM2835) += bcm2711-rp
  25                               bcm2837-rpi-cm3-io3.dtb
  26
  27  subdir-y       += bcm4908
  28 +subdir-y       += bcmbca
  29  subdir-y       += northstar2
  30  subdir-y       += stingray
  31 --- /dev/null
  32 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  33 @@ -0,0 +1,2 @@
  34 +# SPDX-License-Identifier: GPL-2.0
  35 +dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb
  36 --- /dev/null
  37 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
  38 @@ -0,0 +1,128 @@
  39 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  40 +/*
  41 + * Copyright 2022 Broadcom Ltd.
  42 + */
  43 +
  44 +#include <dt-bindings/interrupt-controller/irq.h>
  45 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  46 +
  47 +/ {
  48 +       compatible = "brcm,bcm63158", "brcm,bcmbca";
  49 +       #address-cells = <2>;
  50 +       #size-cells = <2>;
  51 +
  52 +       interrupt-parent = <&gic>;
  53 +
  54 +       cpus {
  55 +               #address-cells = <2>;
  56 +               #size-cells = <0>;
  57 +
  58 +               B53_0: cpu@0 {
  59 +                       compatible = "brcm,brahma-b53";
  60 +                       device_type = "cpu";
  61 +                       reg = <0x0 0x0>;
  62 +                       next-level-cache = <&L2_0>;
  63 +                       enable-method = "psci";
  64 +               };
  65 +
  66 +               B53_1: cpu@1 {
  67 +                       compatible = "brcm,brahma-b53";
  68 +                       device_type = "cpu";
  69 +                       reg = <0x0 0x1>;
  70 +                       next-level-cache = <&L2_0>;
  71 +                       enable-method = "psci";
  72 +               };
  73 +
  74 +               B53_2: cpu@2 {
  75 +                       compatible = "brcm,brahma-b53";
  76 +                       device_type = "cpu";
  77 +                       reg = <0x0 0x2>;
  78 +                       next-level-cache = <&L2_0>;
  79 +                       enable-method = "psci";
  80 +               };
  81 +
  82 +               B53_3: cpu@3 {
  83 +                       compatible = "brcm,brahma-b53";
  84 +                       device_type = "cpu";
  85 +                       reg = <0x0 0x3>;
  86 +                       next-level-cache = <&L2_0>;
  87 +                       enable-method = "psci";
  88 +               };
  89 +
  90 +               L2_0: l2-cache0 {
  91 +                       compatible = "cache";
  92 +               };
  93 +       };
  94 +
  95 +       timer {
  96 +               compatible = "arm,armv8-timer";
  97 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  98 +                       <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  99 +                       <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
 100 +                       <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
 101 +       };
 102 +
 103 +       pmu: pmu {
 104 +               compatible = "arm,cortex-a53-pmu";
 105 +               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 106 +                       <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
 107 +                       <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 108 +                       <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
 109 +               interrupt-affinity = <&B53_0>, <&B53_1>,
 110 +                       <&B53_2>, <&B53_3>;
 111 +       };
 112 +
 113 +       clocks: clocks {
 114 +               periph_clk: periph-clk {
 115 +                       compatible = "fixed-clock";
 116 +                       #clock-cells = <0>;
 117 +                       clock-frequency = <200000000>;
 118 +               };
 119 +               uart_clk: uart-clk {
 120 +                       compatible = "fixed-factor-clock";
 121 +                       #clock-cells = <0>;
 122 +                       clocks = <&periph_clk>;
 123 +                       clock-div = <4>;
 124 +                       clock-mult = <1>;
 125 +               };
 126 +       };
 127 +
 128 +       psci {
 129 +               compatible = "arm,psci-0.2";
 130 +               method = "smc";
 131 +       };
 132 +
 133 +       axi@81000000 {
 134 +               compatible = "simple-bus";
 135 +               #address-cells = <1>;
 136 +               #size-cells = <1>;
 137 +               ranges = <0x0 0x0 0x81000000 0x8000>;
 138 +
 139 +               gic: interrupt-controller@1000 {
 140 +                       compatible = "arm,gic-400";
 141 +                       #interrupt-cells = <3>;
 142 +                       interrupt-controller;
 143 +                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 144 +                       reg = <0x1000 0x1000>,
 145 +                               <0x2000 0x2000>,
 146 +                               <0x4000 0x2000>,
 147 +                               <0x6000 0x2000>;
 148 +               };
 149 +       };
 150 +
 151 +       bus@ff800000 {
 152 +               compatible = "simple-bus";
 153 +               #address-cells = <1>;
 154 +               #size-cells = <1>;
 155 +               ranges = <0x0 0x0 0xff800000 0x800000>;
 156 +
 157 +               uart0: serial@12000 {
 158 +                       compatible = "arm,pl011", "arm,primecell";
 159 +                       reg = <0x12000 0x1000>;
 160 +                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 161 +                       clocks = <&uart_clk>, <&uart_clk>;
 162 +                       clock-names = "uartclk", "apb_pclk";
 163 +                       status = "disabled";
 164 +               };
 165 +       };
 166 +};
 167 --- /dev/null
 168 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm963158.dts
 169 @@ -0,0 +1,30 @@
 170 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 171 +/*
 172 + * Copyright 2022 Broadcom Ltd.
 173 + */
 174 +
 175 +/dts-v1/;
 176 +
 177 +#include "bcm63158.dtsi"
 178 +
 179 +/ {
 180 +       model = "Broadcom BCM963158 Reference Board";
 181 +       compatible = "brcm,bcm963158", "brcm,bcm63158", "brcm,bcmbca";
 182 +
 183 +       aliases {
 184 +               serial0 = &uart0;
 185 +       };
 186 +
 187 +       chosen {
 188 +               stdout-path = "serial0:115200n8";
 189 +       };
 190 +
 191 +       memory@0 {
 192 +               device_type = "memory";
 193 +               reg = <0x0 0x0 0x0 0x08000000>;
 194 +       };
 195 +};
 196 +
 197 +&uart0 {
 198 +       status = "okay";
 199 +};