git.openwrt.org Git - openwrt/staging/ldir.git/blob

   1 From 0b33246dfb59df34b2b834eb00f7aea75cbd4366 Mon Sep 17 00:00:00 2001
   2 From: Zidan Wang <zidan.wang@freescale.com>
   3 Date: Mon, 9 Nov 2015 19:03:13 +0800
   4 Subject: [PATCH] ASoC: fsl-sai: set xCR4/xCR5/xMR for SAI master mode
   5
   6 For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
   7 generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
   8 RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
   9 error sometimes.
  10
  11 Signed-off-by: Zidan Wang <zidan.wang@freescale.com>
  12 Acked-by: Nicolin Chen <nicoleotsuka@gmail.com>
  13 Signed-off-by: Mark Brown <broonie@kernel.org>
  14 (cherry picked from commit 51659ca069ce5bdf20675a7967a39ef8419e87f2)
  15 ---
  16  sound/soc/fsl/fsl_sai.c | 29 +++++++++++++++++++++++++++++
  17  1 file changed, 29 insertions(+)
  18
  19 --- a/sound/soc/fsl/fsl_sai.c
  20 +++ b/sound/soc/fsl/fsl_sai.c
  21 @@ -476,6 +476,35 @@ static int fsl_sai_hw_params(struct snd_
  22                 }
  23         }
  24
  25 +       /*
  26 +        * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will
  27 +        * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4),
  28 +        * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync
  29 +        * error.
  30 +        */
  31 +
  32 +       if (!sai->is_slave_mode) {
  33 +               if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) {
  34 +                       regmap_update_bits(sai->regmap, FSL_SAI_TCR4,
  35 +                               FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
  36 +                               val_cr4);
  37 +                       regmap_update_bits(sai->regmap, FSL_SAI_TCR5,
  38 +                               FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
  39 +                               FSL_SAI_CR5_FBT_MASK, val_cr5);
  40 +                       regmap_write(sai->regmap, FSL_SAI_TMR,
  41 +                               ~0UL - ((1 << channels) - 1));
  42 +               } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) {
  43 +                       regmap_update_bits(sai->regmap, FSL_SAI_RCR4,
  44 +                               FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
  45 +                               val_cr4);
  46 +                       regmap_update_bits(sai->regmap, FSL_SAI_RCR5,
  47 +                               FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK |
  48 +                               FSL_SAI_CR5_FBT_MASK, val_cr5);
  49 +                       regmap_write(sai->regmap, FSL_SAI_RMR,
  50 +                               ~0UL - ((1 << channels) - 1));
  51 +               }
  52 +       }
  53 +
  54         regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx),
  55                            FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK,
  56                            val_cr4);