git.openwrt.org Git - openwrt/staging/jow.git/blob

   1 From f9ecde8dc380769d1477f01416d2e3a65c4fd881 Mon Sep 17 00:00:00 2001
   2 From: Luo Jie <quic_luoj@quicinc.com>
   3 Date: Thu, 7 Nov 2024 17:50:23 +0800
   4 Subject: [PATCH 2/5] clk: qcom: Add CMN PLL clock controller driver for IPQ
   5  SoC
   6
   7 The CMN PLL clock controller supplies clocks to the hardware
   8 blocks that together make up the Ethernet function on Qualcomm
   9 IPQ SoCs and to GCC. The driver is initially supported for
  10 IPQ9574 SoC.
  11
  12 The CMN PLL clock controller expects a reference input clock
  13 from the on-board Wi-Fi block acting as clock source. The input
  14 reference clock needs to be configured to one of the supported
  15 clock rates.
  16
  17 The controller supplies a number of fixed-rate output clocks.
  18 For the IPQ9574, there is one output clock of 353 MHZ to PPE
  19 (Packet Process Engine) hardware block, three 50 MHZ output
  20 clocks and an additional 25 MHZ output clock supplied to the
  21 connected Ethernet devices. The PLL also supplies a 24 MHZ
  22 clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25
  23 MHZ clock to PCS.
  24
  25 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
  26 ---
  27  drivers/clk/qcom/Kconfig       |   9 +
  28  drivers/clk/qcom/Makefile      |   1 +
  29  drivers/clk/qcom/ipq-cmn-pll.c | 436 +++++++++++++++++++++++++++++++++
  30  3 files changed, 446 insertions(+)
  31  create mode 100644 drivers/clk/qcom/ipq-cmn-pll.c
  32
  33 diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
  34 index b9a5cc9fd8c8..3cc7156f881d 100644
  35 --- a/drivers/clk/qcom/Kconfig
  36 +++ b/drivers/clk/qcom/Kconfig
  37 @@ -190,6 +190,15 @@ config IPQ_APSS_6018
  38           Say Y if you want to support CPU frequency scaling on
  39           ipq based devices.
  40
  41 +config IPQ_CMN_PLL
  42 +       tristate "IPQ CMN PLL Clock Controller"
  43 +       help
  44 +         Support for CMN PLL clock controller on IPQ platform. The
  45 +         CMN PLL consumes the AHB/SYS clocks from GCC and supplies
  46 +         the output clocks to the networking hardware and GCC blocks.
  47 +         Say Y or M if you want to support CMN PLL clock on the IPQ
  48 +         based devices.
  49 +
  50  config IPQ_GCC_4019
  51         tristate "IPQ4019 Global Clock Controller"
  52         help
  53 diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
  54 index 65b825a54c45..d12ed80a3021 100644
  55 --- a/drivers/clk/qcom/Makefile
  56 +++ b/drivers/clk/qcom/Makefile
  57 @@ -29,6 +29,7 @@ obj-$(CONFIG_CLK_X1E80100_TCSRCC) += tcsrcc-x1e80100.o
  58  obj-$(CONFIG_CLK_QCM2290_GPUCC) += gpucc-qcm2290.o
  59  obj-$(CONFIG_IPQ_APSS_PLL) += apss-ipq-pll.o
  60  obj-$(CONFIG_IPQ_APSS_6018) += apss-ipq6018.o
  61 +obj-$(CONFIG_IPQ_CMN_PLL) += ipq-cmn-pll.o
  62  obj-$(CONFIG_IPQ_GCC_4019) += gcc-ipq4019.o
  63  obj-$(CONFIG_IPQ_GCC_5018) += gcc-ipq5018.o
  64  obj-$(CONFIG_IPQ_GCC_5332) += gcc-ipq5332.o
  65 diff --git a/drivers/clk/qcom/ipq-cmn-pll.c b/drivers/clk/qcom/ipq-cmn-pll.c
  66 new file mode 100644
  67 index 000000000000..1da8a4a9a8d5
  68 --- /dev/null
  69 +++ b/drivers/clk/qcom/ipq-cmn-pll.c
  70 @@ -0,0 +1,436 @@
  71 +// SPDX-License-Identifier: GPL-2.0-only
  72 +/*
  73 + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
  74 + */
  75 +
  76 +/*
  77 + * CMN PLL block expects the reference clock from on-board Wi-Fi block,
  78 + * and supplies fixed rate clocks as output to the networking hardware
  79 + * blocks and to GCC. The networking related blocks include PPE (packet
  80 + * process engine), the externally connected PHY or switch devices, and
  81 + * the PCS.
  82 + *
  83 + * On the IPQ9574 SoC, there are three clocks with 50 MHZ and one clock
  84 + * with 25 MHZ which are output from the CMN PLL to Ethernet PHY (or switch),
  85 + * and one clock with 353 MHZ to PPE. The other fixed rate output clocks
  86 + * are supplied to GCC (24 MHZ as XO and 32 KHZ as sleep clock), and to PCS
  87 + * with 31.25 MHZ.
  88 + *
  89 + *               +---------+
  90 + *               |   GCC   |
  91 + *               +--+---+--+
  92 + *           AHB CLK|   |SYS CLK
  93 + *                  V   V
  94 + *          +-------+---+------+
  95 + *          |                  +-------------> eth0-50mhz
  96 + * REF CLK  |     IPQ9574      |
  97 + * -------->+                  +-------------> eth1-50mhz
  98 + *          |  CMN PLL block   |
  99 + *          |                  +-------------> eth2-50mhz
 100 + *          |                  |
 101 + *          +----+----+----+---+-------------> eth-25mhz
 102 + *               |    |    |
 103 + *               V    V    V
 104 + *              GCC  PCS  NSS/PPE
 105 + */
 106 +
 107 +#include <linux/bitfield.h>
 108 +#include <linux/clk-provider.h>
 109 +#include <linux/delay.h>
 110 +#include <linux/err.h>
 111 +#include <linux/mod_devicetable.h>
 112 +#include <linux/module.h>
 113 +#include <linux/platform_device.h>
 114 +#include <linux/pm_clock.h>
 115 +#include <linux/pm_runtime.h>
 116 +#include <linux/regmap.h>
 117 +
 118 +#include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
 119 +
 120 +#define CMN_PLL_REFCLK_SRC_SELECTION           0x28
 121 +#define CMN_PLL_REFCLK_SRC_DIV                 GENMASK(9, 8)
 122 +
 123 +#define CMN_PLL_LOCKED                         0x64
 124 +#define CMN_PLL_CLKS_LOCKED                    BIT(8)
 125 +
 126 +#define CMN_PLL_POWER_ON_AND_RESET             0x780
 127 +#define CMN_ANA_EN_SW_RSTN                     BIT(6)
 128 +
 129 +#define CMN_PLL_REFCLK_CONFIG                  0x784
 130 +#define CMN_PLL_REFCLK_EXTERNAL                        BIT(9)
 131 +#define CMN_PLL_REFCLK_DIV                     GENMASK(8, 4)
 132 +#define CMN_PLL_REFCLK_INDEX                   GENMASK(3, 0)
 133 +
 134 +#define CMN_PLL_CTRL                           0x78c
 135 +#define CMN_PLL_CTRL_LOCK_DETECT_EN            BIT(15)
 136 +
 137 +#define CMN_PLL_DIVIDER_CTRL                   0x794
 138 +#define CMN_PLL_DIVIDER_CTRL_FACTOR            GENMASK(9, 0)
 139 +
 140 +/**
 141 + * struct cmn_pll_fixed_output_clk - CMN PLL output clocks information
 142 + * @id:        Clock specifier to be supplied
 143 + * @name: Clock name to be registered
 144 + * @rate: Clock rate
 145 + */
 146 +struct cmn_pll_fixed_output_clk {
 147 +       unsigned int id;
 148 +       const char *name;
 149 +       unsigned long rate;
 150 +};
 151 +
 152 +/**
 153 + * struct clk_cmn_pll - CMN PLL hardware specific data
 154 + * @regmap: hardware regmap.
 155 + * @hw: handle between common and hardware-specific interfaces
 156 + */
 157 +struct clk_cmn_pll {
 158 +       struct regmap *regmap;
 159 +       struct clk_hw hw;
 160 +};
 161 +
 162 +#define CLK_PLL_OUTPUT(_id, _name, _rate) {            \
 163 +       .id =           _id,                            \
 164 +       .name =         _name,                          \
 165 +       .rate =         _rate,                          \
 166 +}
 167 +
 168 +#define to_clk_cmn_pll(_hw) container_of(_hw, struct clk_cmn_pll, hw)
 169 +
 170 +static const struct regmap_config ipq_cmn_pll_regmap_config = {
 171 +       .reg_bits = 32,
 172 +       .reg_stride = 4,
 173 +       .val_bits = 32,
 174 +       .max_register = 0x7fc,
 175 +       .fast_io = true,
 176 +};
 177 +
 178 +static const struct cmn_pll_fixed_output_clk ipq9574_output_clks[] = {
 179 +       CLK_PLL_OUTPUT(XO_24MHZ_CLK, "xo-24mhz", 24000000UL),
 180 +       CLK_PLL_OUTPUT(SLEEP_32KHZ_CLK, "sleep-32khz", 32000UL),
 181 +       CLK_PLL_OUTPUT(PCS_31P25MHZ_CLK, "pcs-31p25mhz", 31250000UL),
 182 +       CLK_PLL_OUTPUT(NSS_1200MHZ_CLK, "nss-1200mhz", 1200000000UL),
 183 +       CLK_PLL_OUTPUT(PPE_353MHZ_CLK, "ppe-353mhz", 353000000UL),
 184 +       CLK_PLL_OUTPUT(ETH0_50MHZ_CLK, "eth0-50mhz", 50000000UL),
 185 +       CLK_PLL_OUTPUT(ETH1_50MHZ_CLK, "eth1-50mhz", 50000000UL),
 186 +       CLK_PLL_OUTPUT(ETH2_50MHZ_CLK, "eth2-50mhz", 50000000UL),
 187 +       CLK_PLL_OUTPUT(ETH_25MHZ_CLK, "eth-25mhz", 25000000UL),
 188 +};
 189 +
 190 +/*
 191 + * CMN PLL has the single parent clock, which supports the several
 192 + * possible parent clock rates, each parent clock rate is reflected
 193 + * by the specific reference index value in the hardware.
 194 + */
 195 +static int ipq_cmn_pll_find_freq_index(unsigned long parent_rate)
 196 +{
 197 +       int index = -EINVAL;
 198 +
 199 +       switch (parent_rate) {
 200 +       case 25000000:
 201 +               index = 3;
 202 +               break;
 203 +       case 31250000:
 204 +               index = 4;
 205 +               break;
 206 +       case 40000000:
 207 +               index = 6;
 208 +               break;
 209 +       case 48000000:
 210 +       case 96000000:
 211 +               /*
 212 +                * Parent clock rate 48 MHZ and 96 MHZ take the same value
 213 +                * of reference clock index. 96 MHZ needs the source clock
 214 +                * divider to be programmed as 2.
 215 +                */
 216 +               index = 7;
 217 +               break;
 218 +       case 50000000:
 219 +               index = 8;
 220 +               break;
 221 +       default:
 222 +               break;
 223 +       }
 224 +
 225 +       return index;
 226 +}
 227 +
 228 +static unsigned long clk_cmn_pll_recalc_rate(struct clk_hw *hw,
 229 +                                            unsigned long parent_rate)
 230 +{
 231 +       struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw);
 232 +       u32 val, factor;
 233 +
 234 +       /*
 235 +        * The value of CMN_PLL_DIVIDER_CTRL_FACTOR is automatically adjusted
 236 +        * by HW according to the parent clock rate.
 237 +        */
 238 +       regmap_read(cmn_pll->regmap, CMN_PLL_DIVIDER_CTRL, &val);
 239 +       factor = FIELD_GET(CMN_PLL_DIVIDER_CTRL_FACTOR, val);
 240 +
 241 +       return parent_rate * 2 * factor;
 242 +}
 243 +
 244 +static int clk_cmn_pll_determine_rate(struct clk_hw *hw,
 245 +                                     struct clk_rate_request *req)
 246 +{
 247 +       int ret;
 248 +
 249 +       /* Validate the rate of the single parent clock. */
 250 +       ret = ipq_cmn_pll_find_freq_index(req->best_parent_rate);
 251 +
 252 +       return ret < 0 ? ret : 0;
 253 +}
 254 +
 255 +/*
 256 + * This function is used to initialize the CMN PLL to enable the fixed
 257 + * rate output clocks. It is expected to be configured once.
 258 + */
 259 +static int clk_cmn_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 260 +                               unsigned long parent_rate)
 261 +{
 262 +       struct clk_cmn_pll *cmn_pll = to_clk_cmn_pll(hw);
 263 +       int ret, index;
 264 +       u32 val;
 265 +
 266 +       /*
 267 +        * Configure the reference input clock selection as per the given
 268 +        * parent clock. The output clock rates are always of fixed value.
 269 +        */
 270 +       index = ipq_cmn_pll_find_freq_index(parent_rate);
 271 +       if (index < 0)
 272 +               return index;
 273 +
 274 +       ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG,
 275 +                                CMN_PLL_REFCLK_INDEX,
 276 +                                FIELD_PREP(CMN_PLL_REFCLK_INDEX, index));
 277 +       if (ret)
 278 +               return ret;
 279 +
 280 +       /*
 281 +        * Update the source clock rate selection and source clock
 282 +        * divider as 2 when the parent clock rate is 96 MHZ.
 283 +        */
 284 +       if (parent_rate == 96000000) {
 285 +               ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_CONFIG,
 286 +                                        CMN_PLL_REFCLK_DIV,
 287 +                                        FIELD_PREP(CMN_PLL_REFCLK_DIV, 2));
 288 +               if (ret)
 289 +                       return ret;
 290 +
 291 +               ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_REFCLK_SRC_SELECTION,
 292 +                                        CMN_PLL_REFCLK_SRC_DIV,
 293 +                                        FIELD_PREP(CMN_PLL_REFCLK_SRC_DIV, 0));
 294 +               if (ret)
 295 +                       return ret;
 296 +       }
 297 +
 298 +       /* Enable PLL locked detect. */
 299 +       ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_CTRL,
 300 +                                CMN_PLL_CTRL_LOCK_DETECT_EN,
 301 +                                CMN_PLL_CTRL_LOCK_DETECT_EN);
 302 +       if (ret)
 303 +               return ret;
 304 +
 305 +       /*
 306 +        * Reset the CMN PLL block to ensure the updated configurations
 307 +        * take effect.
 308 +        */
 309 +       ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET,
 310 +                                CMN_ANA_EN_SW_RSTN, 0);
 311 +       if (ret)
 312 +               return ret;
 313 +
 314 +       usleep_range(1000, 1200);
 315 +       ret = regmap_update_bits(cmn_pll->regmap, CMN_PLL_POWER_ON_AND_RESET,
 316 +                                CMN_ANA_EN_SW_RSTN, CMN_ANA_EN_SW_RSTN);
 317 +       if (ret)
 318 +               return ret;
 319 +
 320 +       /* Stability check of CMN PLL output clocks. */
 321 +       return regmap_read_poll_timeout(cmn_pll->regmap, CMN_PLL_LOCKED, val,
 322 +                                       (val & CMN_PLL_CLKS_LOCKED),
 323 +                                       100, 100 * USEC_PER_MSEC);
 324 +}
 325 +
 326 +static const struct clk_ops clk_cmn_pll_ops = {
 327 +       .recalc_rate = clk_cmn_pll_recalc_rate,
 328 +       .determine_rate = clk_cmn_pll_determine_rate,
 329 +       .set_rate = clk_cmn_pll_set_rate,
 330 +};
 331 +
 332 +static struct clk_hw *ipq_cmn_pll_clk_hw_register(struct platform_device *pdev)
 333 +{
 334 +       struct clk_parent_data pdata = { .index = 0 };
 335 +       struct device *dev = &pdev->dev;
 336 +       struct clk_init_data init = {};
 337 +       struct clk_cmn_pll *cmn_pll;
 338 +       struct regmap *regmap;
 339 +       void __iomem *base;
 340 +       int ret;
 341 +
 342 +       base = devm_platform_ioremap_resource(pdev, 0);
 343 +       if (IS_ERR(base))
 344 +               return ERR_CAST(base);
 345 +
 346 +       regmap = devm_regmap_init_mmio(dev, base, &ipq_cmn_pll_regmap_config);
 347 +       if (IS_ERR(regmap))
 348 +               return ERR_CAST(regmap);
 349 +
 350 +       cmn_pll = devm_kzalloc(dev, sizeof(*cmn_pll), GFP_KERNEL);
 351 +       if (!cmn_pll)
 352 +               return ERR_PTR(-ENOMEM);
 353 +
 354 +       init.name = "cmn_pll";
 355 +       init.parent_data = &pdata;
 356 +       init.num_parents = 1;
 357 +       init.ops = &clk_cmn_pll_ops;
 358 +
 359 +       cmn_pll->hw.init = &init;
 360 +       cmn_pll->regmap = regmap;
 361 +
 362 +       ret = devm_clk_hw_register(dev, &cmn_pll->hw);
 363 +       if (ret)
 364 +               return ERR_PTR(ret);
 365 +
 366 +       return &cmn_pll->hw;
 367 +}
 368 +
 369 +static int ipq_cmn_pll_register_clks(struct platform_device *pdev)
 370 +{
 371 +       const struct cmn_pll_fixed_output_clk *fixed_clk;
 372 +       struct clk_hw_onecell_data *hw_data;
 373 +       struct device *dev = &pdev->dev;
 374 +       struct clk_hw *cmn_pll_hw;
 375 +       unsigned int num_clks;
 376 +       struct clk_hw *hw;
 377 +       int ret, i;
 378 +
 379 +       fixed_clk = ipq9574_output_clks;
 380 +       num_clks = ARRAY_SIZE(ipq9574_output_clks);
 381 +
 382 +       hw_data = devm_kzalloc(dev, struct_size(hw_data, hws, num_clks + 1),
 383 +                              GFP_KERNEL);
 384 +       if (!hw_data)
 385 +               return -ENOMEM;
 386 +
 387 +       /*
 388 +        * Register the CMN PLL clock, which is the parent clock of
 389 +        * the fixed rate output clocks.
 390 +        */
 391 +       cmn_pll_hw = ipq_cmn_pll_clk_hw_register(pdev);
 392 +       if (IS_ERR(cmn_pll_hw))
 393 +               return PTR_ERR(cmn_pll_hw);
 394 +
 395 +       /* Register the fixed rate output clocks. */
 396 +       for (i = 0; i < num_clks; i++) {
 397 +               hw = clk_hw_register_fixed_rate_parent_hw(dev, fixed_clk[i].name,
 398 +                                                         cmn_pll_hw, 0,
 399 +                                                         fixed_clk[i].rate);
 400 +               if (IS_ERR(hw)) {
 401 +                       ret = PTR_ERR(hw);
 402 +                       goto unregister_fixed_clk;
 403 +               }
 404 +
 405 +               hw_data->hws[fixed_clk[i].id] = hw;
 406 +       }
 407 +
 408 +       /*
 409 +        * Provide the CMN PLL clock. The clock rate of CMN PLL
 410 +        * is configured to 12 GHZ by DT property assigned-clock-rates-u64.
 411 +        */
 412 +       hw_data->hws[CMN_PLL_CLK] = cmn_pll_hw;
 413 +       hw_data->num = num_clks + 1;
 414 +
 415 +       ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, hw_data);
 416 +       if (ret)
 417 +               goto unregister_fixed_clk;
 418 +
 419 +       platform_set_drvdata(pdev, hw_data);
 420 +
 421 +       return 0;
 422 +
 423 +unregister_fixed_clk:
 424 +       while (i > 0)
 425 +               clk_hw_unregister(hw_data->hws[fixed_clk[--i].id]);
 426 +
 427 +       return ret;
 428 +}
 429 +
 430 +static int ipq_cmn_pll_clk_probe(struct platform_device *pdev)
 431 +{
 432 +       struct device *dev = &pdev->dev;
 433 +       int ret;
 434 +
 435 +       ret = devm_pm_runtime_enable(dev);
 436 +       if (ret)
 437 +               return ret;
 438 +
 439 +       ret = devm_pm_clk_create(dev);
 440 +       if (ret)
 441 +               return ret;
 442 +
 443 +       /*
 444 +        * To access the CMN PLL registers, the GCC AHB & SYSY clocks
 445 +        * of CMN PLL block need to be enabled.
 446 +        */
 447 +       ret = pm_clk_add(dev, "ahb");
 448 +       if (ret)
 449 +               return dev_err_probe(dev, ret, "Fail to add AHB clock\n");
 450 +
 451 +       ret = pm_clk_add(dev, "sys");
 452 +       if (ret)
 453 +               return dev_err_probe(dev, ret, "Fail to add SYS clock\n");
 454 +
 455 +       ret = pm_runtime_resume_and_get(dev);
 456 +       if (ret)
 457 +               return ret;
 458 +
 459 +       /* Register CMN PLL clock and fixed rate output clocks. */
 460 +       ret = ipq_cmn_pll_register_clks(pdev);
 461 +       pm_runtime_put(dev);
 462 +       if (ret)
 463 +               return dev_err_probe(dev, ret,
 464 +                                    "Fail to register CMN PLL clocks\n");
 465 +
 466 +       return 0;
 467 +}
 468 +
 469 +static void ipq_cmn_pll_clk_remove(struct platform_device *pdev)
 470 +{
 471 +       struct clk_hw_onecell_data *hw_data = platform_get_drvdata(pdev);
 472 +       int i;
 473 +
 474 +       /*
 475 +        * The clock with index CMN_PLL_CLK is unregistered by
 476 +        * device management.
 477 +        */
 478 +       for (i = 0; i < hw_data->num; i++) {
 479 +               if (i != CMN_PLL_CLK)
 480 +                       clk_hw_unregister(hw_data->hws[i]);
 481 +       }
 482 +}
 483 +
 484 +static const struct dev_pm_ops ipq_cmn_pll_pm_ops = {
 485 +       SET_RUNTIME_PM_OPS(pm_clk_suspend, pm_clk_resume, NULL)
 486 +};
 487 +
 488 +static const struct of_device_id ipq_cmn_pll_clk_ids[] = {
 489 +       { .compatible = "qcom,ipq9574-cmn-pll", },
 490 +       { }
 491 +};
 492 +MODULE_DEVICE_TABLE(of, ipq_cmn_pll_clk_ids);
 493 +
 494 +static struct platform_driver ipq_cmn_pll_clk_driver = {
 495 +       .probe = ipq_cmn_pll_clk_probe,
 496 +       .remove_new = ipq_cmn_pll_clk_remove,
 497 +       .driver = {
 498 +               .name = "ipq_cmn_pll",
 499 +               .of_match_table = ipq_cmn_pll_clk_ids,
 500 +               .pm = &ipq_cmn_pll_pm_ops,
 501 +       },
 502 +};
 503 +module_platform_driver(ipq_cmn_pll_clk_driver);
 504 +
 505 +MODULE_DESCRIPTION("Qualcomm Technologies, Inc. IPQ CMN PLL Driver");
 506 +MODULE_LICENSE("GPL");
 507 --
 508 2.45.2
 509