git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From 7ff82416de8295c61423ef6fd75f052d3837d2f7 Mon Sep 17 00:00:00 2001
   2 From: Alexander Couzens <lynxis@fe80.eu>
   3 Date: Wed, 1 Feb 2023 19:23:29 +0100
   4 Subject: [PATCH 11/13] net: mediatek: sgmii: ensure the SGMII PHY is powered
   5  down on configuration
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 The code expect the PHY to be in power down which is only true after reset.
  11 Allow changes of the SGMII parameters more than once.
  12
  13 Only power down when reconfiguring to avoid bouncing the link when there's
  14 no reason to - based on code from Russell King.
  15
  16 There are cases when the SGMII_PHYA_PWD register contains 0x9 which
  17 prevents SGMII from working. The SGMII still shows link but no traffic
  18 can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
  19 taken from a good working state of the SGMII interface.
  20
  21 Fixes: 42c03844e93d ("net-next: mediatek: add support for MediaTek MT7622 SoC")
  22 Suggested-by: Russell King (Oracle) <linux@armlinux.org.uk>
  23 Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
  24 [ bmork: rebased and squashed into one patch ]
  25 Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
  26 Signed-off-by: Bjørn Mork <bjorn@mork.no>
  27 Acked-by: Daniel Golle <daniel@makrotopia.org>
  28 Tested-by: Daniel Golle <daniel@makrotopia.org>
  29 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  30 ---
  31  drivers/net/ethernet/mediatek/mtk_eth_soc.h |  2 ++
  32  drivers/net/ethernet/mediatek/mtk_sgmii.c   | 39 +++++++++++++++------
  33  2 files changed, 30 insertions(+), 11 deletions(-)
  34
  35 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  36 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
  37 @@ -1070,11 +1070,13 @@ struct mtk_soc_data {
  38   * @regmap:            The register map pointing at the range used to setup
  39   *                     SGMII modes
  40   * @ana_rgc3:          The offset refers to register ANA_RGC3 related to regmap
  41 + * @interface:         Currently configured interface mode
  42   * @pcs:               Phylink PCS structure
  43   */
  44  struct mtk_pcs {
  45         struct regmap   *regmap;
  46         u32             ana_rgc3;
  47 +       phy_interface_t interface;
  48         struct phylink_pcs pcs;
  49  };
  50
  51 --- a/drivers/net/ethernet/mediatek/mtk_sgmii.c
  52 +++ b/drivers/net/ethernet/mediatek/mtk_sgmii.c
  53 @@ -43,11 +43,6 @@ static int mtk_pcs_config(struct phylink
  54         int advertise, link_timer;
  55         bool changed, use_an;
  56
  57 -       if (interface == PHY_INTERFACE_MODE_2500BASEX)
  58 -               rgc3 = RG_PHY_SPEED_3_125G;
  59 -       else
  60 -               rgc3 = 0;
  61 -
  62         advertise = phylink_mii_c22_pcs_encode_advertisement(interface,
  63                                                              advertising);
  64         if (advertise < 0)
  65 @@ -88,9 +83,22 @@ static int mtk_pcs_config(struct phylink
  66                 bmcr = 0;
  67         }
  68
  69 -       /* Configure the underlying interface speed */
  70 -       regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
  71 -                          RG_PHY_SPEED_3_125G, rgc3);
  72 +       if (mpcs->interface != interface) {
  73 +               /* PHYA power down */
  74 +               regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
  75 +                                  SGMII_PHYA_PWD, SGMII_PHYA_PWD);
  76 +
  77 +               if (interface == PHY_INTERFACE_MODE_2500BASEX)
  78 +                       rgc3 = RG_PHY_SPEED_3_125G;
  79 +               else
  80 +                       rgc3 = 0;
  81 +
  82 +               /* Configure the underlying interface speed */
  83 +               regmap_update_bits(mpcs->regmap, mpcs->ana_rgc3,
  84 +                                  RG_PHY_SPEED_3_125G, rgc3);
  85 +
  86 +               mpcs->interface = interface;
  87 +       }
  88
  89         /* Update the advertisement, noting whether it has changed */
  90         regmap_update_bits_check(mpcs->regmap, SGMSYS_PCS_ADVERTISE,
  91 @@ -108,9 +116,17 @@ static int mtk_pcs_config(struct phylink
  92         regmap_update_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1,
  93                            SGMII_AN_RESTART | SGMII_AN_ENABLE, bmcr);
  94
  95 -       /* Release PHYA power down state */
  96 -       regmap_update_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL,
  97 -                          SGMII_PHYA_PWD, 0);
  98 +       /* Release PHYA power down state
  99 +        * Only removing bit SGMII_PHYA_PWD isn't enough.
 100 +        * There are cases when the SGMII_PHYA_PWD register contains 0x9 which
 101 +        * prevents SGMII from working. The SGMII still shows link but no traffic
 102 +        * can flow. Writing 0x0 to the PHYA_PWD register fix the issue. 0x0 was
 103 +        * taken from a good working state of the SGMII interface.
 104 +        * Unknown how much the QPHY needs but it is racy without a sleep.
 105 +        * Tested on mt7622 & mt7986.
 106 +        */
 107 +       usleep_range(50, 100);
 108 +       regmap_write(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, 0);
 109
 110         return changed;
 111  }
 112 @@ -171,6 +187,7 @@ int mtk_sgmii_init(struct mtk_sgmii *ss,
 113                         return PTR_ERR(ss->pcs[i].regmap);
 114
 115                 ss->pcs[i].pcs.ops = &mtk_pcs_ops;
 116 +               ss->pcs[i].interface = PHY_INTERFACE_MODE_NA;
 117         }
 118
 119         return 0;