git.openwrt.org Git - openwrt/staging/xback.git/blob

   1 From c0f1cbf795095c21b92a46fa1dc47a7b787ce538 Mon Sep 17 00:00:00 2001
   2 From: Luo Jie <quic_luoj@quicinc.com>
   3 Date: Fri, 3 Jan 2025 15:31:34 +0800
   4 Subject: [PATCH 1/3] dt-bindings: clock: qcom: Add CMN PLL clock controller
   5  for IPQ SoC
   6
   7 The CMN PLL controller provides clocks to networking hardware blocks
   8 and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the
   9 on-chip Wi-Fi, and produces output clocks at fixed rates. These output
  10 rates are predetermined, and are unrelated to the input clock rate.
  11 The primary purpose of CMN PLL is to supply clocks to the networking
  12 hardware such as PPE (packet process engine), PCS and the externally
  13 connected switch or PHY device. The CMN PLL block also outputs fixed
  14 rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep
  15 clock supplied to GCC.
  16
  17 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
  18 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  19 Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com
  20 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
  21 ---
  22  .../bindings/clock/qcom,ipq9574-cmn-pll.yaml  | 77 +++++++++++++++++++
  23  include/dt-bindings/clock/qcom,ipq-cmn-pll.h  | 22 ++++++
  24  2 files changed, 99 insertions(+)
  25  create mode 100644 Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
  26  create mode 100644 include/dt-bindings/clock/qcom,ipq-cmn-pll.h
  27
  28 diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
  29 new file mode 100644
  30 index 000000000000..f869b3739be8
  31 --- /dev/null
  32 +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml
  33 @@ -0,0 +1,77 @@
  34 +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
  35 +%YAML 1.2
  36 +---
  37 +$id: http://devicetree.org/schemas/clock/qcom,ipq9574-cmn-pll.yaml#
  38 +$schema: http://devicetree.org/meta-schemas/core.yaml#
  39 +
  40 +title: Qualcomm CMN PLL Clock Controller on IPQ SoC
  41 +
  42 +maintainers:
  43 +  - Bjorn Andersson <andersson@kernel.org>
  44 +  - Luo Jie <quic_luoj@quicinc.com>
  45 +
  46 +description:
  47 +  The CMN (or common) PLL clock controller expects a reference
  48 +  input clock. This reference clock is from the on-board Wi-Fi.
  49 +  The CMN PLL supplies a number of fixed rate output clocks to
  50 +  the devices providing networking functions and to GCC. These
  51 +  networking hardware include PPE (packet process engine), PCS
  52 +  and the externally connected switch or PHY devices. The CMN
  53 +  PLL block also outputs fixed rate clocks to GCC. The PLL's
  54 +  primary function is to enable fixed rate output clocks for
  55 +  networking hardware functions used with the IPQ SoC.
  56 +
  57 +properties:
  58 +  compatible:
  59 +    enum:
  60 +      - qcom,ipq9574-cmn-pll
  61 +
  62 +  reg:
  63 +    maxItems: 1
  64 +
  65 +  clocks:
  66 +    items:
  67 +      - description: The reference clock. The supported clock rates include
  68 +          25000000, 31250000, 40000000, 48000000, 50000000 and 96000000 HZ.
  69 +      - description: The AHB clock
  70 +      - description: The SYS clock
  71 +    description:
  72 +      The reference clock is the source clock of CMN PLL, which is from the
  73 +      Wi-Fi. The AHB and SYS clocks must be enabled to access CMN PLL
  74 +      clock registers.
  75 +
  76 +  clock-names:
  77 +    items:
  78 +      - const: ref
  79 +      - const: ahb
  80 +      - const: sys
  81 +
  82 +  "#clock-cells":
  83 +    const: 1
  84 +
  85 +required:
  86 +  - compatible
  87 +  - reg
  88 +  - clocks
  89 +  - clock-names
  90 +  - "#clock-cells"
  91 +
  92 +additionalProperties: false
  93 +
  94 +examples:
  95 +  - |
  96 +    #include <dt-bindings/clock/qcom,ipq-cmn-pll.h>
  97 +    #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
  98 +
  99 +    cmn_pll: clock-controller@9b000 {
 100 +        compatible = "qcom,ipq9574-cmn-pll";
 101 +        reg = <0x0009b000 0x800>;
 102 +        clocks = <&cmn_pll_ref_clk>,
 103 +                 <&gcc GCC_CMN_12GPLL_AHB_CLK>,
 104 +                 <&gcc GCC_CMN_12GPLL_SYS_CLK>;
 105 +        clock-names = "ref", "ahb", "sys";
 106 +        #clock-cells = <1>;
 107 +        assigned-clocks = <&cmn_pll CMN_PLL_CLK>;
 108 +        assigned-clock-rates-u64 = /bits/ 64 <12000000000>;
 109 +    };
 110 +...
 111 diff --git a/include/dt-bindings/clock/qcom,ipq-cmn-pll.h b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
 112 new file mode 100644
 113 index 000000000000..936e92b3b62c
 114 --- /dev/null
 115 +++ b/include/dt-bindings/clock/qcom,ipq-cmn-pll.h
 116 @@ -0,0 +1,22 @@
 117 +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
 118 +/*
 119 + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
 120 + */
 121 +
 122 +#ifndef _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
 123 +#define _DT_BINDINGS_CLK_QCOM_IPQ_CMN_PLL_H
 124 +
 125 +/* CMN PLL core clock. */
 126 +#define CMN_PLL_CLK                    0
 127 +
 128 +/* The output clocks from CMN PLL of IPQ9574. */
 129 +#define XO_24MHZ_CLK                   1
 130 +#define SLEEP_32KHZ_CLK                        2
 131 +#define PCS_31P25MHZ_CLK               3
 132 +#define NSS_1200MHZ_CLK                        4
 133 +#define PPE_353MHZ_CLK                 5
 134 +#define ETH0_50MHZ_CLK                 6
 135 +#define ETH1_50MHZ_CLK                 7
 136 +#define ETH2_50MHZ_CLK                 8
 137 +#define ETH_25MHZ_CLK                  9
 138 +#endif
 139 --
 140 2.47.1
 141