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1 From 9e56ff53b4115875667760445b028357848b4748 Mon Sep 17 00:00:00 2001
2 From: Christian Marangi <ansuelsmth@gmail.com>
3 Date: Mon, 29 Jan 2024 15:15:19 +0100
4 Subject: [PATCH 1/5] net: phy: move at803x PHY driver to dedicated directory
5
6 In preparation for addition of other Qcom PHY and to tidy things up,
7 move the at803x PHY driver to dedicated directory.
8
9 The same order in the Kconfig selection is saved.
10
11 Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
12 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
13 Link: https://lore.kernel.org/r/20240129141600.2592-2-ansuelsmth@gmail.com
14 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
15 ---
16 drivers/net/phy/Kconfig | 7 +------
17 drivers/net/phy/Makefile | 2 +-
18 drivers/net/phy/qcom/Kconfig | 7 +++++++
19 drivers/net/phy/qcom/Makefile | 2 ++
20 drivers/net/phy/{ => qcom}/at803x.c | 0
21 5 files changed, 11 insertions(+), 7 deletions(-)
22 create mode 100644 drivers/net/phy/qcom/Kconfig
23 create mode 100644 drivers/net/phy/qcom/Makefile
24 rename drivers/net/phy/{ => qcom}/at803x.c (100%)
25
26 --- a/drivers/net/phy/Kconfig
27 +++ b/drivers/net/phy/Kconfig
28 @@ -277,12 +277,7 @@ config NXP_TJA11XX_PHY
29 help
30 Currently supports the NXP TJA1100 and TJA1101 PHY.
31
32 -config AT803X_PHY
33 - tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
34 - depends on REGULATOR
35 - help
36 - Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
37 - QCA8337(Internal qca8k PHY) model
38 +source "drivers/net/phy/qcom/Kconfig"
39
40 config QSEMI_PHY
41 tristate "Quality Semiconductor PHYs"
42 --- a/drivers/net/phy/Makefile
43 +++ b/drivers/net/phy/Makefile
44 @@ -34,7 +34,6 @@ obj-$(CONFIG_ADIN_PHY) += adin.o
45 obj-$(CONFIG_ADIN1100_PHY) += adin1100.o
46 obj-$(CONFIG_AMD_PHY) += amd.o
47 obj-$(CONFIG_AQUANTIA_PHY) += aquantia/
48 -obj-$(CONFIG_AT803X_PHY) += at803x.o
49 obj-$(CONFIG_AX88796B_PHY) += ax88796b.o
50 obj-$(CONFIG_BCM54140_PHY) += bcm54140.o
51 obj-$(CONFIG_BCM63XX_PHY) += bcm63xx.o
52 @@ -75,6 +74,7 @@ obj-$(CONFIG_MOTORCOMM_PHY) += motorcomm
53 obj-$(CONFIG_NATIONAL_PHY) += national.o
54 obj-$(CONFIG_NXP_C45_TJA11XX_PHY) += nxp-c45-tja11xx.o
55 obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o
56 +obj-y += qcom/
57 obj-$(CONFIG_QSEMI_PHY) += qsemi.o
58 obj-$(CONFIG_REALTEK_PHY) += realtek.o
59 obj-$(CONFIG_RENESAS_PHY) += uPD60620.o
60 --- /dev/null
61 +++ b/drivers/net/phy/qcom/Kconfig
62 @@ -0,0 +1,7 @@
63 +# SPDX-License-Identifier: GPL-2.0-only
64 +config AT803X_PHY
65 + tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
66 + depends on REGULATOR
67 + help
68 + Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
69 + QCA8337(Internal qca8k PHY) model
70 --- /dev/null
71 +++ b/drivers/net/phy/qcom/Makefile
72 @@ -0,0 +1,2 @@
73 +# SPDX-License-Identifier: GPL-2.0
74 +obj-$(CONFIG_AT803X_PHY) += at803x.o
75 --- a/drivers/net/phy/at803x.c
76 +++ /dev/null
77 @@ -1,2759 +0,0 @@
78 -// SPDX-License-Identifier: GPL-2.0+
79 -/*
80 - * drivers/net/phy/at803x.c
81 - *
82 - * Driver for Qualcomm Atheros AR803x PHY
83 - *
84 - * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
85 - */
86 -
87 -#include <linux/phy.h>
88 -#include <linux/module.h>
89 -#include <linux/string.h>
90 -#include <linux/netdevice.h>
91 -#include <linux/etherdevice.h>
92 -#include <linux/ethtool_netlink.h>
93 -#include <linux/bitfield.h>
94 -#include <linux/regulator/of_regulator.h>
95 -#include <linux/regulator/driver.h>
96 -#include <linux/regulator/consumer.h>
97 -#include <linux/of.h>
98 -#include <linux/phylink.h>
99 -#include <linux/sfp.h>
100 -#include <dt-bindings/net/qca-ar803x.h>
101 -
102 -#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
103 -#define AT803X_SFC_ASSERT_CRS BIT(11)
104 -#define AT803X_SFC_FORCE_LINK BIT(10)
105 -#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5)
106 -#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3
107 -#define AT803X_SFC_MANUAL_MDIX 0x1
108 -#define AT803X_SFC_MANUAL_MDI 0x0
109 -#define AT803X_SFC_SQE_TEST BIT(2)
110 -#define AT803X_SFC_POLARITY_REVERSAL BIT(1)
111 -#define AT803X_SFC_DISABLE_JABBER BIT(0)
112 -
113 -#define AT803X_SPECIFIC_STATUS 0x11
114 -#define AT803X_SS_SPEED_MASK GENMASK(15, 14)
115 -#define AT803X_SS_SPEED_1000 2
116 -#define AT803X_SS_SPEED_100 1
117 -#define AT803X_SS_SPEED_10 0
118 -#define AT803X_SS_DUPLEX BIT(13)
119 -#define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11)
120 -#define AT803X_SS_MDIX BIT(6)
121 -
122 -#define QCA808X_SS_SPEED_MASK GENMASK(9, 7)
123 -#define QCA808X_SS_SPEED_2500 4
124 -
125 -#define AT803X_INTR_ENABLE 0x12
126 -#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
127 -#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
128 -#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
129 -#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
130 -#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
131 -#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
132 -#define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8)
133 -#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7)
134 -#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
135 -#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
136 -#define AT803X_INTR_ENABLE_WOL BIT(0)
137 -
138 -#define AT803X_INTR_STATUS 0x13
139 -
140 -#define AT803X_SMART_SPEED 0x14
141 -#define AT803X_SMART_SPEED_ENABLE BIT(5)
142 -#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2)
143 -#define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1)
144 -#define AT803X_CDT 0x16
145 -#define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8)
146 -#define AT803X_CDT_ENABLE_TEST BIT(0)
147 -#define AT803X_CDT_STATUS 0x1c
148 -#define AT803X_CDT_STATUS_STAT_NORMAL 0
149 -#define AT803X_CDT_STATUS_STAT_SHORT 1
150 -#define AT803X_CDT_STATUS_STAT_OPEN 2
151 -#define AT803X_CDT_STATUS_STAT_FAIL 3
152 -#define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8)
153 -#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0)
154 -#define AT803X_LED_CONTROL 0x18
155 -
156 -#define AT803X_PHY_MMD3_WOL_CTRL 0x8012
157 -#define AT803X_WOL_EN BIT(5)
158 -#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
159 -#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
160 -#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
161 -#define AT803X_REG_CHIP_CONFIG 0x1f
162 -#define AT803X_BT_BX_REG_SEL 0x8000
163 -
164 -#define AT803X_DEBUG_ADDR 0x1D
165 -#define AT803X_DEBUG_DATA 0x1E
166 -
167 -#define AT803X_MODE_CFG_MASK 0x0F
168 -#define AT803X_MODE_CFG_BASET_RGMII 0x00
169 -#define AT803X_MODE_CFG_BASET_SGMII 0x01
170 -#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02
171 -#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03
172 -#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04
173 -#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05
174 -#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06
175 -#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07
176 -#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B
177 -#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E
178 -#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F
179 -
180 -#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
181 -#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
182 -
183 -#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
184 -#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
185 -#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
186 -#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
187 -
188 -#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
189 -#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
190 -
191 -#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
192 -#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
193 -#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
194 -#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
195 -
196 -#define AT803X_DEBUG_REG_3C 0x3C
197 -
198 -#define AT803X_DEBUG_REG_GREEN 0x3D
199 -#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6)
200 -
201 -#define AT803X_DEBUG_REG_1F 0x1F
202 -#define AT803X_DEBUG_PLL_ON BIT(2)
203 -#define AT803X_DEBUG_RGMII_1V8 BIT(3)
204 -
205 -#define MDIO_AZ_DEBUG 0x800D
206 -
207 -/* AT803x supports either the XTAL input pad, an internal PLL or the
208 - * DSP as clock reference for the clock output pad. The XTAL reference
209 - * is only used for 25 MHz output, all other frequencies need the PLL.
210 - * The DSP as a clock reference is used in synchronous ethernet
211 - * applications.
212 - *
213 - * By default the PLL is only enabled if there is a link. Otherwise
214 - * the PHY will go into low power state and disabled the PLL. You can
215 - * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
216 - * enabled.
217 - */
218 -#define AT803X_MMD7_CLK25M 0x8016
219 -#define AT803X_CLK_OUT_MASK GENMASK(4, 2)
220 -#define AT803X_CLK_OUT_25MHZ_XTAL 0
221 -#define AT803X_CLK_OUT_25MHZ_DSP 1
222 -#define AT803X_CLK_OUT_50MHZ_PLL 2
223 -#define AT803X_CLK_OUT_50MHZ_DSP 3
224 -#define AT803X_CLK_OUT_62_5MHZ_PLL 4
225 -#define AT803X_CLK_OUT_62_5MHZ_DSP 5
226 -#define AT803X_CLK_OUT_125MHZ_PLL 6
227 -#define AT803X_CLK_OUT_125MHZ_DSP 7
228 -
229 -/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
230 - * but doesn't support choosing between XTAL/PLL and DSP.
231 - */
232 -#define AT8035_CLK_OUT_MASK GENMASK(4, 3)
233 -
234 -#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
235 -#define AT803X_CLK_OUT_STRENGTH_FULL 0
236 -#define AT803X_CLK_OUT_STRENGTH_HALF 1
237 -#define AT803X_CLK_OUT_STRENGTH_QUARTER 2
238 -
239 -#define AT803X_DEFAULT_DOWNSHIFT 5
240 -#define AT803X_MIN_DOWNSHIFT 2
241 -#define AT803X_MAX_DOWNSHIFT 9
242 -
243 -#define AT803X_MMD3_SMARTEEE_CTL1 0x805b
244 -#define AT803X_MMD3_SMARTEEE_CTL2 0x805c
245 -#define AT803X_MMD3_SMARTEEE_CTL3 0x805d
246 -#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8)
247 -
248 -#define ATH9331_PHY_ID 0x004dd041
249 -#define ATH8030_PHY_ID 0x004dd076
250 -#define ATH8031_PHY_ID 0x004dd074
251 -#define ATH8032_PHY_ID 0x004dd023
252 -#define ATH8035_PHY_ID 0x004dd072
253 -#define AT8030_PHY_ID_MASK 0xffffffef
254 -
255 -#define QCA8081_PHY_ID 0x004dd101
256 -
257 -#define QCA8327_A_PHY_ID 0x004dd033
258 -#define QCA8327_B_PHY_ID 0x004dd034
259 -#define QCA8337_PHY_ID 0x004dd036
260 -#define QCA9561_PHY_ID 0x004dd042
261 -#define QCA8K_PHY_ID_MASK 0xffffffff
262 -
263 -#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0)
264 -
265 -#define AT803X_PAGE_FIBER 0
266 -#define AT803X_PAGE_COPPER 1
267 -
268 -/* don't turn off internal PLL */
269 -#define AT803X_KEEP_PLL_ENABLED BIT(0)
270 -#define AT803X_DISABLE_SMARTEEE BIT(1)
271 -
272 -/* disable hibernation mode */
273 -#define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
274 -
275 -/* ADC threshold */
276 -#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80
277 -#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0)
278 -#define QCA808X_ADC_THRESHOLD_80MV 0
279 -#define QCA808X_ADC_THRESHOLD_100MV 0xf0
280 -#define QCA808X_ADC_THRESHOLD_200MV 0x0f
281 -#define QCA808X_ADC_THRESHOLD_300MV 0xff
282 -
283 -/* CLD control */
284 -#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007
285 -#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4)
286 -#define QCA808X_8023AZ_AFE_EN 0x90
287 -
288 -/* AZ control */
289 -#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008
290 -#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32
291 -
292 -#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014
293 -#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529
294 -
295 -#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E
296 -#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341
297 -
298 -#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E
299 -#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419
300 -
301 -#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020
302 -#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341
303 -
304 -#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c
305 -#define QCA808X_TOP_OPTION1_DATA 0x0
306 -
307 -#define QCA808X_PHY_MMD3_DEBUG_1 0xa100
308 -#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203
309 -#define QCA808X_PHY_MMD3_DEBUG_2 0xa101
310 -#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad
311 -#define QCA808X_PHY_MMD3_DEBUG_3 0xa103
312 -#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698
313 -#define QCA808X_PHY_MMD3_DEBUG_4 0xa105
314 -#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001
315 -#define QCA808X_PHY_MMD3_DEBUG_5 0xa106
316 -#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111
317 -#define QCA808X_PHY_MMD3_DEBUG_6 0xa011
318 -#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85
319 -
320 -/* master/slave seed config */
321 -#define QCA808X_PHY_DEBUG_LOCAL_SEED 9
322 -#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1)
323 -#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2)
324 -#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32
325 -
326 -/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
327 - * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
328 - */
329 -#define QCA808X_DBG_AN_TEST 0xb
330 -#define QCA808X_HIBERNATION_EN BIT(15)
331 -
332 -#define QCA808X_CDT_ENABLE_TEST BIT(15)
333 -#define QCA808X_CDT_INTER_CHECK_DIS BIT(13)
334 -#define QCA808X_CDT_STATUS BIT(11)
335 -#define QCA808X_CDT_LENGTH_UNIT BIT(10)
336 -
337 -#define QCA808X_MMD3_CDT_STATUS 0x8064
338 -#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065
339 -#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066
340 -#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067
341 -#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068
342 -#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8)
343 -#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0)
344 -
345 -#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12)
346 -#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8)
347 -#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4)
348 -#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0)
349 -
350 -#define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0)
351 -#define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
352 -#define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
353 -#define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
354 -#define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
355 -
356 -#define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2)
357 -#define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
358 -#define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
359 -#define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
360 -
361 -/* NORMAL are MDI with type set to 0 */
362 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI1
363 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
364 - QCA808X_CDT_STATUS_STAT_MDI1)
365 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
366 - QCA808X_CDT_STATUS_STAT_MDI1)
367 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI2
368 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
369 - QCA808X_CDT_STATUS_STAT_MDI2)
370 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
371 - QCA808X_CDT_STATUS_STAT_MDI2)
372 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI3
373 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
374 - QCA808X_CDT_STATUS_STAT_MDI3)
375 -#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
376 - QCA808X_CDT_STATUS_STAT_MDI3)
377 -
378 -/* Added for reference of existence but should be handled by wait_for_completion already */
379 -#define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3))
380 -
381 -#define QCA808X_MMD7_LED_GLOBAL 0x8073
382 -#define QCA808X_LED_BLINK_1 GENMASK(11, 6)
383 -#define QCA808X_LED_BLINK_2 GENMASK(5, 0)
384 -/* Values are the same for both BLINK_1 and BLINK_2 */
385 -#define QCA808X_LED_BLINK_FREQ_MASK GENMASK(5, 3)
386 -#define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
387 -#define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
388 -#define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
389 -#define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
390 -#define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
391 -#define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
392 -#define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
393 -#define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
394 -#define QCA808X_LED_BLINK_DUTY_MASK GENMASK(2, 0)
395 -#define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
396 -#define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
397 -#define QCA808X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
398 -#define QCA808X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
399 -#define QCA808X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
400 -#define QCA808X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
401 -#define QCA808X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
402 -#define QCA808X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
403 -
404 -#define QCA808X_MMD7_LED2_CTRL 0x8074
405 -#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075
406 -#define QCA808X_MMD7_LED1_CTRL 0x8076
407 -#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077
408 -#define QCA808X_MMD7_LED0_CTRL 0x8078
409 -#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2))
410 -
411 -/* LED hw control pattern is the same for every LED */
412 -#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0)
413 -#define QCA808X_LED_SPEED2500_ON BIT(15)
414 -#define QCA808X_LED_SPEED2500_BLINK BIT(14)
415 -/* Follow blink trigger even if duplex or speed condition doesn't match */
416 -#define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13)
417 -#define QCA808X_LED_FULL_DUPLEX_ON BIT(12)
418 -#define QCA808X_LED_HALF_DUPLEX_ON BIT(11)
419 -#define QCA808X_LED_TX_BLINK BIT(10)
420 -#define QCA808X_LED_RX_BLINK BIT(9)
421 -#define QCA808X_LED_TX_ON_10MS BIT(8)
422 -#define QCA808X_LED_RX_ON_10MS BIT(7)
423 -#define QCA808X_LED_SPEED1000_ON BIT(6)
424 -#define QCA808X_LED_SPEED100_ON BIT(5)
425 -#define QCA808X_LED_SPEED10_ON BIT(4)
426 -#define QCA808X_LED_COLLISION_BLINK BIT(3)
427 -#define QCA808X_LED_SPEED1000_BLINK BIT(2)
428 -#define QCA808X_LED_SPEED100_BLINK BIT(1)
429 -#define QCA808X_LED_SPEED10_BLINK BIT(0)
430 -
431 -#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079
432 -#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2))
433 -
434 -/* LED force ctrl is the same for every LED
435 - * No documentation exist for this, not even internal one
436 - * with NDA as QCOM gives only info about configuring
437 - * hw control pattern rules and doesn't indicate any way
438 - * to force the LED to specific mode.
439 - * These define comes from reverse and testing and maybe
440 - * lack of some info or some info are not entirely correct.
441 - * For the basic LED control and hw control these finding
442 - * are enough to support LED control in all the required APIs.
443 - *
444 - * On doing some comparison with implementation with qca807x,
445 - * it was found that it's 1:1 equal to it and confirms all the
446 - * reverse done. It was also found further specification with the
447 - * force mode and the blink modes.
448 - */
449 -#define QCA808X_LED_FORCE_EN BIT(15)
450 -#define QCA808X_LED_FORCE_MODE_MASK GENMASK(14, 13)
451 -#define QCA808X_LED_FORCE_BLINK_1 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
452 -#define QCA808X_LED_FORCE_BLINK_2 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
453 -#define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
454 -#define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
455 -
456 -#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a
457 -/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
458 - * LED to active high. It's not clear what BIT 3 and BIT 4 does.
459 - */
460 -#define QCA808X_LED_ACTIVE_HIGH BIT(6)
461 -
462 -/* QCA808X 1G chip type */
463 -#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d
464 -#define QCA808X_PHY_CHIP_TYPE_1G BIT(0)
465 -
466 -#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072
467 -#define QCA8081_PHY_FIFO_RSTN BIT(11)
468 -
469 -MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
470 -MODULE_AUTHOR("Matus Ujhelyi");
471 -MODULE_LICENSE("GPL");
472 -
473 -enum stat_access_type {
474 - PHY,
475 - MMD
476 -};
477 -
478 -struct at803x_hw_stat {
479 - const char *string;
480 - u8 reg;
481 - u32 mask;
482 - enum stat_access_type access_type;
483 -};
484 -
485 -static struct at803x_hw_stat qca83xx_hw_stats[] = {
486 - { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
487 - { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
488 - { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
489 -};
490 -
491 -struct at803x_ss_mask {
492 - u16 speed_mask;
493 - u8 speed_shift;
494 -};
495 -
496 -struct at803x_priv {
497 - int flags;
498 - u16 clk_25m_reg;
499 - u16 clk_25m_mask;
500 - u8 smarteee_lpi_tw_1g;
501 - u8 smarteee_lpi_tw_100m;
502 - bool is_fiber;
503 - bool is_1000basex;
504 - struct regulator_dev *vddio_rdev;
505 - struct regulator_dev *vddh_rdev;
506 - u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
507 - int led_polarity_mode;
508 -};
509 -
510 -struct at803x_context {
511 - u16 bmcr;
512 - u16 advertise;
513 - u16 control1000;
514 - u16 int_enable;
515 - u16 smart_speed;
516 - u16 led_control;
517 -};
518 -
519 -static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
520 -{
521 - int ret;
522 -
523 - ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
524 - if (ret < 0)
525 - return ret;
526 -
527 - return phy_write(phydev, AT803X_DEBUG_DATA, data);
528 -}
529 -
530 -static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
531 -{
532 - int ret;
533 -
534 - ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
535 - if (ret < 0)
536 - return ret;
537 -
538 - return phy_read(phydev, AT803X_DEBUG_DATA);
539 -}
540 -
541 -static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
542 - u16 clear, u16 set)
543 -{
544 - u16 val;
545 - int ret;
546 -
547 - ret = at803x_debug_reg_read(phydev, reg);
548 - if (ret < 0)
549 - return ret;
550 -
551 - val = ret & 0xffff;
552 - val &= ~clear;
553 - val |= set;
554 -
555 - return phy_write(phydev, AT803X_DEBUG_DATA, val);
556 -}
557 -
558 -static int at803x_write_page(struct phy_device *phydev, int page)
559 -{
560 - int mask;
561 - int set;
562 -
563 - if (page == AT803X_PAGE_COPPER) {
564 - set = AT803X_BT_BX_REG_SEL;
565 - mask = 0;
566 - } else {
567 - set = 0;
568 - mask = AT803X_BT_BX_REG_SEL;
569 - }
570 -
571 - return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
572 -}
573 -
574 -static int at803x_read_page(struct phy_device *phydev)
575 -{
576 - int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
577 -
578 - if (ccr < 0)
579 - return ccr;
580 -
581 - if (ccr & AT803X_BT_BX_REG_SEL)
582 - return AT803X_PAGE_COPPER;
583 -
584 - return AT803X_PAGE_FIBER;
585 -}
586 -
587 -static int at803x_enable_rx_delay(struct phy_device *phydev)
588 -{
589 - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
590 - AT803X_DEBUG_RX_CLK_DLY_EN);
591 -}
592 -
593 -static int at803x_enable_tx_delay(struct phy_device *phydev)
594 -{
595 - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
596 - AT803X_DEBUG_TX_CLK_DLY_EN);
597 -}
598 -
599 -static int at803x_disable_rx_delay(struct phy_device *phydev)
600 -{
601 - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
602 - AT803X_DEBUG_RX_CLK_DLY_EN, 0);
603 -}
604 -
605 -static int at803x_disable_tx_delay(struct phy_device *phydev)
606 -{
607 - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
608 - AT803X_DEBUG_TX_CLK_DLY_EN, 0);
609 -}
610 -
611 -/* save relevant PHY registers to private copy */
612 -static void at803x_context_save(struct phy_device *phydev,
613 - struct at803x_context *context)
614 -{
615 - context->bmcr = phy_read(phydev, MII_BMCR);
616 - context->advertise = phy_read(phydev, MII_ADVERTISE);
617 - context->control1000 = phy_read(phydev, MII_CTRL1000);
618 - context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
619 - context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
620 - context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
621 -}
622 -
623 -/* restore relevant PHY registers from private copy */
624 -static void at803x_context_restore(struct phy_device *phydev,
625 - const struct at803x_context *context)
626 -{
627 - phy_write(phydev, MII_BMCR, context->bmcr);
628 - phy_write(phydev, MII_ADVERTISE, context->advertise);
629 - phy_write(phydev, MII_CTRL1000, context->control1000);
630 - phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
631 - phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
632 - phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
633 -}
634 -
635 -static int at803x_set_wol(struct phy_device *phydev,
636 - struct ethtool_wolinfo *wol)
637 -{
638 - int ret, irq_enabled;
639 -
640 - if (wol->wolopts & WAKE_MAGIC) {
641 - struct net_device *ndev = phydev->attached_dev;
642 - const u8 *mac;
643 - unsigned int i;
644 - static const unsigned int offsets[] = {
645 - AT803X_LOC_MAC_ADDR_32_47_OFFSET,
646 - AT803X_LOC_MAC_ADDR_16_31_OFFSET,
647 - AT803X_LOC_MAC_ADDR_0_15_OFFSET,
648 - };
649 -
650 - if (!ndev)
651 - return -ENODEV;
652 -
653 - mac = (const u8 *)ndev->dev_addr;
654 -
655 - if (!is_valid_ether_addr(mac))
656 - return -EINVAL;
657 -
658 - for (i = 0; i < 3; i++)
659 - phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
660 - mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
661 -
662 - /* Enable WOL interrupt */
663 - ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
664 - if (ret)
665 - return ret;
666 - } else {
667 - /* Disable WOL interrupt */
668 - ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
669 - if (ret)
670 - return ret;
671 - }
672 -
673 - /* Clear WOL status */
674 - ret = phy_read(phydev, AT803X_INTR_STATUS);
675 - if (ret < 0)
676 - return ret;
677 -
678 - /* Check if there are other interrupts except for WOL triggered when PHY is
679 - * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
680 - * be passed up to the interrupt PIN.
681 - */
682 - irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
683 - if (irq_enabled < 0)
684 - return irq_enabled;
685 -
686 - irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
687 - if (ret & irq_enabled && !phy_polling_mode(phydev))
688 - phy_trigger_machine(phydev);
689 -
690 - return 0;
691 -}
692 -
693 -static void at803x_get_wol(struct phy_device *phydev,
694 - struct ethtool_wolinfo *wol)
695 -{
696 - int value;
697 -
698 - wol->supported = WAKE_MAGIC;
699 - wol->wolopts = 0;
700 -
701 - value = phy_read(phydev, AT803X_INTR_ENABLE);
702 - if (value < 0)
703 - return;
704 -
705 - if (value & AT803X_INTR_ENABLE_WOL)
706 - wol->wolopts |= WAKE_MAGIC;
707 -}
708 -
709 -static int qca83xx_get_sset_count(struct phy_device *phydev)
710 -{
711 - return ARRAY_SIZE(qca83xx_hw_stats);
712 -}
713 -
714 -static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
715 -{
716 - int i;
717 -
718 - for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
719 - strscpy(data + i * ETH_GSTRING_LEN,
720 - qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
721 - }
722 -}
723 -
724 -static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
725 -{
726 - struct at803x_hw_stat stat = qca83xx_hw_stats[i];
727 - struct at803x_priv *priv = phydev->priv;
728 - int val;
729 - u64 ret;
730 -
731 - if (stat.access_type == MMD)
732 - val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
733 - else
734 - val = phy_read(phydev, stat.reg);
735 -
736 - if (val < 0) {
737 - ret = U64_MAX;
738 - } else {
739 - val = val & stat.mask;
740 - priv->stats[i] += val;
741 - ret = priv->stats[i];
742 - }
743 -
744 - return ret;
745 -}
746 -
747 -static void qca83xx_get_stats(struct phy_device *phydev,
748 - struct ethtool_stats *stats, u64 *data)
749 -{
750 - int i;
751 -
752 - for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
753 - data[i] = qca83xx_get_stat(phydev, i);
754 -}
755 -
756 -static int at803x_suspend(struct phy_device *phydev)
757 -{
758 - int value;
759 - int wol_enabled;
760 -
761 - value = phy_read(phydev, AT803X_INTR_ENABLE);
762 - wol_enabled = value & AT803X_INTR_ENABLE_WOL;
763 -
764 - if (wol_enabled)
765 - value = BMCR_ISOLATE;
766 - else
767 - value = BMCR_PDOWN;
768 -
769 - phy_modify(phydev, MII_BMCR, 0, value);
770 -
771 - return 0;
772 -}
773 -
774 -static int at803x_resume(struct phy_device *phydev)
775 -{
776 - return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
777 -}
778 -
779 -static int at803x_parse_dt(struct phy_device *phydev)
780 -{
781 - struct device_node *node = phydev->mdio.dev.of_node;
782 - struct at803x_priv *priv = phydev->priv;
783 - u32 freq, strength, tw;
784 - unsigned int sel;
785 - int ret;
786 -
787 - if (!IS_ENABLED(CONFIG_OF_MDIO))
788 - return 0;
789 -
790 - if (of_property_read_bool(node, "qca,disable-smarteee"))
791 - priv->flags |= AT803X_DISABLE_SMARTEEE;
792 -
793 - if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
794 - priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
795 -
796 - if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
797 - if (!tw || tw > 255) {
798 - phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
799 - return -EINVAL;
800 - }
801 - priv->smarteee_lpi_tw_1g = tw;
802 - }
803 -
804 - if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
805 - if (!tw || tw > 255) {
806 - phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
807 - return -EINVAL;
808 - }
809 - priv->smarteee_lpi_tw_100m = tw;
810 - }
811 -
812 - ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
813 - if (!ret) {
814 - switch (freq) {
815 - case 25000000:
816 - sel = AT803X_CLK_OUT_25MHZ_XTAL;
817 - break;
818 - case 50000000:
819 - sel = AT803X_CLK_OUT_50MHZ_PLL;
820 - break;
821 - case 62500000:
822 - sel = AT803X_CLK_OUT_62_5MHZ_PLL;
823 - break;
824 - case 125000000:
825 - sel = AT803X_CLK_OUT_125MHZ_PLL;
826 - break;
827 - default:
828 - phydev_err(phydev, "invalid qca,clk-out-frequency\n");
829 - return -EINVAL;
830 - }
831 -
832 - priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
833 - priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
834 - }
835 -
836 - ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
837 - if (!ret) {
838 - priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
839 - switch (strength) {
840 - case AR803X_STRENGTH_FULL:
841 - priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
842 - break;
843 - case AR803X_STRENGTH_HALF:
844 - priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
845 - break;
846 - case AR803X_STRENGTH_QUARTER:
847 - priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
848 - break;
849 - default:
850 - phydev_err(phydev, "invalid qca,clk-out-strength\n");
851 - return -EINVAL;
852 - }
853 - }
854 -
855 - return 0;
856 -}
857 -
858 -static int at803x_probe(struct phy_device *phydev)
859 -{
860 - struct device *dev = &phydev->mdio.dev;
861 - struct at803x_priv *priv;
862 - int ret;
863 -
864 - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
865 - if (!priv)
866 - return -ENOMEM;
867 -
868 - /* Init LED polarity mode to -1 */
869 - priv->led_polarity_mode = -1;
870 -
871 - phydev->priv = priv;
872 -
873 - ret = at803x_parse_dt(phydev);
874 - if (ret)
875 - return ret;
876 -
877 - return 0;
878 -}
879 -
880 -static int at803x_get_features(struct phy_device *phydev)
881 -{
882 - struct at803x_priv *priv = phydev->priv;
883 - int err;
884 -
885 - err = genphy_read_abilities(phydev);
886 - if (err)
887 - return err;
888 -
889 - if (phydev->drv->phy_id != ATH8031_PHY_ID)
890 - return 0;
891 -
892 - /* AR8031/AR8033 have different status registers
893 - * for copper and fiber operation. However, the
894 - * extended status register is the same for both
895 - * operation modes.
896 - *
897 - * As a result of that, ESTATUS_1000_XFULL is set
898 - * to 1 even when operating in copper TP mode.
899 - *
900 - * Remove this mode from the supported link modes
901 - * when not operating in 1000BaseX mode.
902 - */
903 - if (!priv->is_1000basex)
904 - linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
905 - phydev->supported);
906 -
907 - return 0;
908 -}
909 -
910 -static int at803x_smarteee_config(struct phy_device *phydev)
911 -{
912 - struct at803x_priv *priv = phydev->priv;
913 - u16 mask = 0, val = 0;
914 - int ret;
915 -
916 - if (priv->flags & AT803X_DISABLE_SMARTEEE)
917 - return phy_modify_mmd(phydev, MDIO_MMD_PCS,
918 - AT803X_MMD3_SMARTEEE_CTL3,
919 - AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
920 -
921 - if (priv->smarteee_lpi_tw_1g) {
922 - mask |= 0xff00;
923 - val |= priv->smarteee_lpi_tw_1g << 8;
924 - }
925 - if (priv->smarteee_lpi_tw_100m) {
926 - mask |= 0x00ff;
927 - val |= priv->smarteee_lpi_tw_100m;
928 - }
929 - if (!mask)
930 - return 0;
931 -
932 - ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
933 - mask, val);
934 - if (ret)
935 - return ret;
936 -
937 - return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
938 - AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
939 - AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
940 -}
941 -
942 -static int at803x_clk_out_config(struct phy_device *phydev)
943 -{
944 - struct at803x_priv *priv = phydev->priv;
945 -
946 - if (!priv->clk_25m_mask)
947 - return 0;
948 -
949 - return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
950 - priv->clk_25m_mask, priv->clk_25m_reg);
951 -}
952 -
953 -static int at8031_pll_config(struct phy_device *phydev)
954 -{
955 - struct at803x_priv *priv = phydev->priv;
956 -
957 - /* The default after hardware reset is PLL OFF. After a soft reset, the
958 - * values are retained.
959 - */
960 - if (priv->flags & AT803X_KEEP_PLL_ENABLED)
961 - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
962 - 0, AT803X_DEBUG_PLL_ON);
963 - else
964 - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
965 - AT803X_DEBUG_PLL_ON, 0);
966 -}
967 -
968 -static int at803x_hibernation_mode_config(struct phy_device *phydev)
969 -{
970 - struct at803x_priv *priv = phydev->priv;
971 -
972 - /* The default after hardware reset is hibernation mode enabled. After
973 - * software reset, the value is retained.
974 - */
975 - if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
976 - return 0;
977 -
978 - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
979 - AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
980 -}
981 -
982 -static int at803x_config_init(struct phy_device *phydev)
983 -{
984 - int ret;
985 -
986 - /* The RX and TX delay default is:
987 - * after HW reset: RX delay enabled and TX delay disabled
988 - * after SW reset: RX delay enabled, while TX delay retains the
989 - * value before reset.
990 - */
991 - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
992 - phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
993 - ret = at803x_enable_rx_delay(phydev);
994 - else
995 - ret = at803x_disable_rx_delay(phydev);
996 - if (ret < 0)
997 - return ret;
998 -
999 - if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
1000 - phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
1001 - ret = at803x_enable_tx_delay(phydev);
1002 - else
1003 - ret = at803x_disable_tx_delay(phydev);
1004 - if (ret < 0)
1005 - return ret;
1006 -
1007 - ret = at803x_smarteee_config(phydev);
1008 - if (ret < 0)
1009 - return ret;
1010 -
1011 - ret = at803x_clk_out_config(phydev);
1012 - if (ret < 0)
1013 - return ret;
1014 -
1015 - ret = at803x_hibernation_mode_config(phydev);
1016 - if (ret < 0)
1017 - return ret;
1018 -
1019 - /* Ar803x extended next page bit is enabled by default. Cisco
1020 - * multigig switches read this bit and attempt to negotiate 10Gbps
1021 - * rates even if the next page bit is disabled. This is incorrect
1022 - * behaviour but we still need to accommodate it. XNP is only needed
1023 - * for 10Gbps support, so disable XNP.
1024 - */
1025 - return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
1026 -}
1027 -
1028 -static int at803x_ack_interrupt(struct phy_device *phydev)
1029 -{
1030 - int err;
1031 -
1032 - err = phy_read(phydev, AT803X_INTR_STATUS);
1033 -
1034 - return (err < 0) ? err : 0;
1035 -}
1036 -
1037 -static int at803x_config_intr(struct phy_device *phydev)
1038 -{
1039 - int err;
1040 - int value;
1041 -
1042 - value = phy_read(phydev, AT803X_INTR_ENABLE);
1043 -
1044 - if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
1045 - /* Clear any pending interrupts */
1046 - err = at803x_ack_interrupt(phydev);
1047 - if (err)
1048 - return err;
1049 -
1050 - value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
1051 - value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
1052 - value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
1053 - value |= AT803X_INTR_ENABLE_LINK_FAIL;
1054 - value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
1055 -
1056 - err = phy_write(phydev, AT803X_INTR_ENABLE, value);
1057 - } else {
1058 - err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
1059 - if (err)
1060 - return err;
1061 -
1062 - /* Clear any pending interrupts */
1063 - err = at803x_ack_interrupt(phydev);
1064 - }
1065 -
1066 - return err;
1067 -}
1068 -
1069 -static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
1070 -{
1071 - int irq_status, int_enabled;
1072 -
1073 - irq_status = phy_read(phydev, AT803X_INTR_STATUS);
1074 - if (irq_status < 0) {
1075 - phy_error(phydev);
1076 - return IRQ_NONE;
1077 - }
1078 -
1079 - /* Read the current enabled interrupts */
1080 - int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
1081 - if (int_enabled < 0) {
1082 - phy_error(phydev);
1083 - return IRQ_NONE;
1084 - }
1085 -
1086 - /* See if this was one of our enabled interrupts */
1087 - if (!(irq_status & int_enabled))
1088 - return IRQ_NONE;
1089 -
1090 - phy_trigger_machine(phydev);
1091 -
1092 - return IRQ_HANDLED;
1093 -}
1094 -
1095 -static void at803x_link_change_notify(struct phy_device *phydev)
1096 -{
1097 - /*
1098 - * Conduct a hardware reset for AT8030 every time a link loss is
1099 - * signalled. This is necessary to circumvent a hardware bug that
1100 - * occurs when the cable is unplugged while TX packets are pending
1101 - * in the FIFO. In such cases, the FIFO enters an error mode it
1102 - * cannot recover from by software.
1103 - */
1104 - if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
1105 - struct at803x_context context;
1106 -
1107 - at803x_context_save(phydev, &context);
1108 -
1109 - phy_device_reset(phydev, 1);
1110 - usleep_range(1000, 2000);
1111 - phy_device_reset(phydev, 0);
1112 - usleep_range(1000, 2000);
1113 -
1114 - at803x_context_restore(phydev, &context);
1115 -
1116 - phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
1117 - }
1118 -}
1119 -
1120 -static int at803x_read_specific_status(struct phy_device *phydev,
1121 - struct at803x_ss_mask ss_mask)
1122 -{
1123 - int ss;
1124 -
1125 - /* Read the AT8035 PHY-Specific Status register, which indicates the
1126 - * speed and duplex that the PHY is actually using, irrespective of
1127 - * whether we are in autoneg mode or not.
1128 - */
1129 - ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
1130 - if (ss < 0)
1131 - return ss;
1132 -
1133 - if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
1134 - int sfc, speed;
1135 -
1136 - sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
1137 - if (sfc < 0)
1138 - return sfc;
1139 -
1140 - speed = ss & ss_mask.speed_mask;
1141 - speed >>= ss_mask.speed_shift;
1142 -
1143 - switch (speed) {
1144 - case AT803X_SS_SPEED_10:
1145 - phydev->speed = SPEED_10;
1146 - break;
1147 - case AT803X_SS_SPEED_100:
1148 - phydev->speed = SPEED_100;
1149 - break;
1150 - case AT803X_SS_SPEED_1000:
1151 - phydev->speed = SPEED_1000;
1152 - break;
1153 - case QCA808X_SS_SPEED_2500:
1154 - phydev->speed = SPEED_2500;
1155 - break;
1156 - }
1157 - if (ss & AT803X_SS_DUPLEX)
1158 - phydev->duplex = DUPLEX_FULL;
1159 - else
1160 - phydev->duplex = DUPLEX_HALF;
1161 -
1162 - if (ss & AT803X_SS_MDIX)
1163 - phydev->mdix = ETH_TP_MDI_X;
1164 - else
1165 - phydev->mdix = ETH_TP_MDI;
1166 -
1167 - switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
1168 - case AT803X_SFC_MANUAL_MDI:
1169 - phydev->mdix_ctrl = ETH_TP_MDI;
1170 - break;
1171 - case AT803X_SFC_MANUAL_MDIX:
1172 - phydev->mdix_ctrl = ETH_TP_MDI_X;
1173 - break;
1174 - case AT803X_SFC_AUTOMATIC_CROSSOVER:
1175 - phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1176 - break;
1177 - }
1178 - }
1179 -
1180 - return 0;
1181 -}
1182 -
1183 -static int at803x_read_status(struct phy_device *phydev)
1184 -{
1185 - struct at803x_ss_mask ss_mask = { 0 };
1186 - int err, old_link = phydev->link;
1187 -
1188 - /* Update the link, but return if there was an error */
1189 - err = genphy_update_link(phydev);
1190 - if (err)
1191 - return err;
1192 -
1193 - /* why bother the PHY if nothing can have changed */
1194 - if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
1195 - return 0;
1196 -
1197 - phydev->speed = SPEED_UNKNOWN;
1198 - phydev->duplex = DUPLEX_UNKNOWN;
1199 - phydev->pause = 0;
1200 - phydev->asym_pause = 0;
1201 -
1202 - err = genphy_read_lpa(phydev);
1203 - if (err < 0)
1204 - return err;
1205 -
1206 - ss_mask.speed_mask = AT803X_SS_SPEED_MASK;
1207 - ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
1208 - err = at803x_read_specific_status(phydev, ss_mask);
1209 - if (err < 0)
1210 - return err;
1211 -
1212 - if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
1213 - phy_resolve_aneg_pause(phydev);
1214 -
1215 - return 0;
1216 -}
1217 -
1218 -static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
1219 -{
1220 - u16 val;
1221 -
1222 - switch (ctrl) {
1223 - case ETH_TP_MDI:
1224 - val = AT803X_SFC_MANUAL_MDI;
1225 - break;
1226 - case ETH_TP_MDI_X:
1227 - val = AT803X_SFC_MANUAL_MDIX;
1228 - break;
1229 - case ETH_TP_MDI_AUTO:
1230 - val = AT803X_SFC_AUTOMATIC_CROSSOVER;
1231 - break;
1232 - default:
1233 - return 0;
1234 - }
1235 -
1236 - return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
1237 - AT803X_SFC_MDI_CROSSOVER_MODE_M,
1238 - FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
1239 -}
1240 -
1241 -static int at803x_prepare_config_aneg(struct phy_device *phydev)
1242 -{
1243 - int ret;
1244 -
1245 - ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
1246 - if (ret < 0)
1247 - return ret;
1248 -
1249 - /* Changes of the midx bits are disruptive to the normal operation;
1250 - * therefore any changes to these registers must be followed by a
1251 - * software reset to take effect.
1252 - */
1253 - if (ret == 1) {
1254 - ret = genphy_soft_reset(phydev);
1255 - if (ret < 0)
1256 - return ret;
1257 - }
1258 -
1259 - return 0;
1260 -}
1261 -
1262 -static int at803x_config_aneg(struct phy_device *phydev)
1263 -{
1264 - struct at803x_priv *priv = phydev->priv;
1265 - int ret;
1266 -
1267 - ret = at803x_prepare_config_aneg(phydev);
1268 - if (ret)
1269 - return ret;
1270 -
1271 - if (priv->is_1000basex)
1272 - return genphy_c37_config_aneg(phydev);
1273 -
1274 - return genphy_config_aneg(phydev);
1275 -}
1276 -
1277 -static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
1278 -{
1279 - int val;
1280 -
1281 - val = phy_read(phydev, AT803X_SMART_SPEED);
1282 - if (val < 0)
1283 - return val;
1284 -
1285 - if (val & AT803X_SMART_SPEED_ENABLE)
1286 - *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
1287 - else
1288 - *d = DOWNSHIFT_DEV_DISABLE;
1289 -
1290 - return 0;
1291 -}
1292 -
1293 -static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
1294 -{
1295 - u16 mask, set;
1296 - int ret;
1297 -
1298 - switch (cnt) {
1299 - case DOWNSHIFT_DEV_DEFAULT_COUNT:
1300 - cnt = AT803X_DEFAULT_DOWNSHIFT;
1301 - fallthrough;
1302 - case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
1303 - set = AT803X_SMART_SPEED_ENABLE |
1304 - AT803X_SMART_SPEED_BYPASS_TIMER |
1305 - FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
1306 - mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
1307 - break;
1308 - case DOWNSHIFT_DEV_DISABLE:
1309 - set = 0;
1310 - mask = AT803X_SMART_SPEED_ENABLE |
1311 - AT803X_SMART_SPEED_BYPASS_TIMER;
1312 - break;
1313 - default:
1314 - return -EINVAL;
1315 - }
1316 -
1317 - ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
1318 -
1319 - /* After changing the smart speed settings, we need to perform a
1320 - * software reset, use phy_init_hw() to make sure we set the
1321 - * reapply any values which might got lost during software reset.
1322 - */
1323 - if (ret == 1)
1324 - ret = phy_init_hw(phydev);
1325 -
1326 - return ret;
1327 -}
1328 -
1329 -static int at803x_get_tunable(struct phy_device *phydev,
1330 - struct ethtool_tunable *tuna, void *data)
1331 -{
1332 - switch (tuna->id) {
1333 - case ETHTOOL_PHY_DOWNSHIFT:
1334 - return at803x_get_downshift(phydev, data);
1335 - default:
1336 - return -EOPNOTSUPP;
1337 - }
1338 -}
1339 -
1340 -static int at803x_set_tunable(struct phy_device *phydev,
1341 - struct ethtool_tunable *tuna, const void *data)
1342 -{
1343 - switch (tuna->id) {
1344 - case ETHTOOL_PHY_DOWNSHIFT:
1345 - return at803x_set_downshift(phydev, *(const u8 *)data);
1346 - default:
1347 - return -EOPNOTSUPP;
1348 - }
1349 -}
1350 -
1351 -static int at803x_cable_test_result_trans(u16 status)
1352 -{
1353 - switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1354 - case AT803X_CDT_STATUS_STAT_NORMAL:
1355 - return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1356 - case AT803X_CDT_STATUS_STAT_SHORT:
1357 - return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1358 - case AT803X_CDT_STATUS_STAT_OPEN:
1359 - return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1360 - case AT803X_CDT_STATUS_STAT_FAIL:
1361 - default:
1362 - return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1363 - }
1364 -}
1365 -
1366 -static bool at803x_cdt_test_failed(u16 status)
1367 -{
1368 - return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
1369 - AT803X_CDT_STATUS_STAT_FAIL;
1370 -}
1371 -
1372 -static bool at803x_cdt_fault_length_valid(u16 status)
1373 -{
1374 - switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
1375 - case AT803X_CDT_STATUS_STAT_OPEN:
1376 - case AT803X_CDT_STATUS_STAT_SHORT:
1377 - return true;
1378 - }
1379 - return false;
1380 -}
1381 -
1382 -static int at803x_cdt_fault_length(int dt)
1383 -{
1384 - /* According to the datasheet the distance to the fault is
1385 - * DELTA_TIME * 0.824 meters.
1386 - *
1387 - * The author suspect the correct formula is:
1388 - *
1389 - * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
1390 - *
1391 - * where c is the speed of light, VF is the velocity factor of
1392 - * the twisted pair cable, 125MHz the counter frequency and
1393 - * we need to divide by 2 because the hardware will measure the
1394 - * round trip time to the fault and back to the PHY.
1395 - *
1396 - * With a VF of 0.69 we get the factor 0.824 mentioned in the
1397 - * datasheet.
1398 - */
1399 - return (dt * 824) / 10;
1400 -}
1401 -
1402 -static int at803x_cdt_start(struct phy_device *phydev,
1403 - u32 cdt_start)
1404 -{
1405 - return phy_write(phydev, AT803X_CDT, cdt_start);
1406 -}
1407 -
1408 -static int at803x_cdt_wait_for_completion(struct phy_device *phydev,
1409 - u32 cdt_en)
1410 -{
1411 - int val, ret;
1412 -
1413 - /* One test run takes about 25ms */
1414 - ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
1415 - !(val & cdt_en),
1416 - 30000, 100000, true);
1417 -
1418 - return ret < 0 ? ret : 0;
1419 -}
1420 -
1421 -static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
1422 -{
1423 - static const int ethtool_pair[] = {
1424 - ETHTOOL_A_CABLE_PAIR_A,
1425 - ETHTOOL_A_CABLE_PAIR_B,
1426 - ETHTOOL_A_CABLE_PAIR_C,
1427 - ETHTOOL_A_CABLE_PAIR_D,
1428 - };
1429 - int ret, val;
1430 -
1431 - val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
1432 - AT803X_CDT_ENABLE_TEST;
1433 - ret = at803x_cdt_start(phydev, val);
1434 - if (ret)
1435 - return ret;
1436 -
1437 - ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
1438 - if (ret)
1439 - return ret;
1440 -
1441 - val = phy_read(phydev, AT803X_CDT_STATUS);
1442 - if (val < 0)
1443 - return val;
1444 -
1445 - if (at803x_cdt_test_failed(val))
1446 - return 0;
1447 -
1448 - ethnl_cable_test_result(phydev, ethtool_pair[pair],
1449 - at803x_cable_test_result_trans(val));
1450 -
1451 - if (at803x_cdt_fault_length_valid(val)) {
1452 - val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
1453 - ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1454 - at803x_cdt_fault_length(val));
1455 - }
1456 -
1457 - return 1;
1458 -}
1459 -
1460 -static int at803x_cable_test_get_status(struct phy_device *phydev,
1461 - bool *finished, unsigned long pair_mask)
1462 -{
1463 - int retries = 20;
1464 - int pair, ret;
1465 -
1466 - *finished = false;
1467 -
1468 - /* According to the datasheet the CDT can be performed when
1469 - * there is no link partner or when the link partner is
1470 - * auto-negotiating. Starting the test will restart the AN
1471 - * automatically. It seems that doing this repeatedly we will
1472 - * get a slot where our link partner won't disturb our
1473 - * measurement.
1474 - */
1475 - while (pair_mask && retries--) {
1476 - for_each_set_bit(pair, &pair_mask, 4) {
1477 - ret = at803x_cable_test_one_pair(phydev, pair);
1478 - if (ret < 0)
1479 - return ret;
1480 - if (ret)
1481 - clear_bit(pair, &pair_mask);
1482 - }
1483 - if (pair_mask)
1484 - msleep(250);
1485 - }
1486 -
1487 - *finished = true;
1488 -
1489 - return 0;
1490 -}
1491 -
1492 -static void at803x_cable_test_autoneg(struct phy_device *phydev)
1493 -{
1494 - /* Enable auto-negotiation, but advertise no capabilities, no link
1495 - * will be established. A restart of the auto-negotiation is not
1496 - * required, because the cable test will automatically break the link.
1497 - */
1498 - phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
1499 - phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
1500 -}
1501 -
1502 -static int at803x_cable_test_start(struct phy_device *phydev)
1503 -{
1504 - at803x_cable_test_autoneg(phydev);
1505 - /* we do all the (time consuming) work later */
1506 - return 0;
1507 -}
1508 -
1509 -static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
1510 - unsigned int selector)
1511 -{
1512 - struct phy_device *phydev = rdev_get_drvdata(rdev);
1513 -
1514 - if (selector)
1515 - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
1516 - 0, AT803X_DEBUG_RGMII_1V8);
1517 - else
1518 - return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
1519 - AT803X_DEBUG_RGMII_1V8, 0);
1520 -}
1521 -
1522 -static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
1523 -{
1524 - struct phy_device *phydev = rdev_get_drvdata(rdev);
1525 - int val;
1526 -
1527 - val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
1528 - if (val < 0)
1529 - return val;
1530 -
1531 - return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
1532 -}
1533 -
1534 -static const struct regulator_ops vddio_regulator_ops = {
1535 - .list_voltage = regulator_list_voltage_table,
1536 - .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
1537 - .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
1538 -};
1539 -
1540 -static const unsigned int vddio_voltage_table[] = {
1541 - 1500000,
1542 - 1800000,
1543 -};
1544 -
1545 -static const struct regulator_desc vddio_desc = {
1546 - .name = "vddio",
1547 - .of_match = of_match_ptr("vddio-regulator"),
1548 - .n_voltages = ARRAY_SIZE(vddio_voltage_table),
1549 - .volt_table = vddio_voltage_table,
1550 - .ops = &vddio_regulator_ops,
1551 - .type = REGULATOR_VOLTAGE,
1552 - .owner = THIS_MODULE,
1553 -};
1554 -
1555 -static const struct regulator_ops vddh_regulator_ops = {
1556 -};
1557 -
1558 -static const struct regulator_desc vddh_desc = {
1559 - .name = "vddh",
1560 - .of_match = of_match_ptr("vddh-regulator"),
1561 - .n_voltages = 1,
1562 - .fixed_uV = 2500000,
1563 - .ops = &vddh_regulator_ops,
1564 - .type = REGULATOR_VOLTAGE,
1565 - .owner = THIS_MODULE,
1566 -};
1567 -
1568 -static int at8031_register_regulators(struct phy_device *phydev)
1569 -{
1570 - struct at803x_priv *priv = phydev->priv;
1571 - struct device *dev = &phydev->mdio.dev;
1572 - struct regulator_config config = { };
1573 -
1574 - config.dev = dev;
1575 - config.driver_data = phydev;
1576 -
1577 - priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
1578 - if (IS_ERR(priv->vddio_rdev)) {
1579 - phydev_err(phydev, "failed to register VDDIO regulator\n");
1580 - return PTR_ERR(priv->vddio_rdev);
1581 - }
1582 -
1583 - priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
1584 - if (IS_ERR(priv->vddh_rdev)) {
1585 - phydev_err(phydev, "failed to register VDDH regulator\n");
1586 - return PTR_ERR(priv->vddh_rdev);
1587 - }
1588 -
1589 - return 0;
1590 -}
1591 -
1592 -static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
1593 -{
1594 - struct phy_device *phydev = upstream;
1595 - __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
1596 - __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
1597 - DECLARE_PHY_INTERFACE_MASK(interfaces);
1598 - phy_interface_t iface;
1599 -
1600 - linkmode_zero(phy_support);
1601 - phylink_set(phy_support, 1000baseX_Full);
1602 - phylink_set(phy_support, 1000baseT_Full);
1603 - phylink_set(phy_support, Autoneg);
1604 - phylink_set(phy_support, Pause);
1605 - phylink_set(phy_support, Asym_Pause);
1606 -
1607 - linkmode_zero(sfp_support);
1608 - sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces);
1609 - /* Some modules support 10G modes as well as others we support.
1610 - * Mask out non-supported modes so the correct interface is picked.
1611 - */
1612 - linkmode_and(sfp_support, phy_support, sfp_support);
1613 -
1614 - if (linkmode_empty(sfp_support)) {
1615 - dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
1616 - return -EINVAL;
1617 - }
1618 -
1619 - iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
1620 -
1621 - /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
1622 - * interface for use with SFP modules.
1623 - * However, some copper modules detected as having a preferred SGMII
1624 - * interface do default to and function in 1000Base-X mode, so just
1625 - * print a warning and allow such modules, as they may have some chance
1626 - * of working.
1627 - */
1628 - if (iface == PHY_INTERFACE_MODE_SGMII)
1629 - dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
1630 - else if (iface != PHY_INTERFACE_MODE_1000BASEX)
1631 - return -EINVAL;
1632 -
1633 - return 0;
1634 -}
1635 -
1636 -static const struct sfp_upstream_ops at8031_sfp_ops = {
1637 - .attach = phy_sfp_attach,
1638 - .detach = phy_sfp_detach,
1639 - .module_insert = at8031_sfp_insert,
1640 -};
1641 -
1642 -static int at8031_parse_dt(struct phy_device *phydev)
1643 -{
1644 - struct device_node *node = phydev->mdio.dev.of_node;
1645 - struct at803x_priv *priv = phydev->priv;
1646 - int ret;
1647 -
1648 - if (of_property_read_bool(node, "qca,keep-pll-enabled"))
1649 - priv->flags |= AT803X_KEEP_PLL_ENABLED;
1650 -
1651 - ret = at8031_register_regulators(phydev);
1652 - if (ret < 0)
1653 - return ret;
1654 -
1655 - ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
1656 - "vddio");
1657 - if (ret) {
1658 - phydev_err(phydev, "failed to get VDDIO regulator\n");
1659 - return ret;
1660 - }
1661 -
1662 - /* Only AR8031/8033 support 1000Base-X for SFP modules */
1663 - return phy_sfp_probe(phydev, &at8031_sfp_ops);
1664 -}
1665 -
1666 -static int at8031_probe(struct phy_device *phydev)
1667 -{
1668 - struct at803x_priv *priv = phydev->priv;
1669 - int mode_cfg;
1670 - int ccr;
1671 - int ret;
1672 -
1673 - ret = at803x_probe(phydev);
1674 - if (ret)
1675 - return ret;
1676 -
1677 - /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
1678 - * options.
1679 - */
1680 - ret = at8031_parse_dt(phydev);
1681 - if (ret)
1682 - return ret;
1683 -
1684 - ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
1685 - if (ccr < 0)
1686 - return ccr;
1687 - mode_cfg = ccr & AT803X_MODE_CFG_MASK;
1688 -
1689 - switch (mode_cfg) {
1690 - case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
1691 - case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
1692 - priv->is_1000basex = true;
1693 - fallthrough;
1694 - case AT803X_MODE_CFG_FX100_RGMII_50OHM:
1695 - case AT803X_MODE_CFG_FX100_RGMII_75OHM:
1696 - priv->is_fiber = true;
1697 - break;
1698 - }
1699 -
1700 - /* Disable WoL in 1588 register which is enabled
1701 - * by default
1702 - */
1703 - return phy_modify_mmd(phydev, MDIO_MMD_PCS,
1704 - AT803X_PHY_MMD3_WOL_CTRL,
1705 - AT803X_WOL_EN, 0);
1706 -}
1707 -
1708 -static int at8031_config_init(struct phy_device *phydev)
1709 -{
1710 - struct at803x_priv *priv = phydev->priv;
1711 - int ret;
1712 -
1713 - /* Some bootloaders leave the fiber page selected.
1714 - * Switch to the appropriate page (fiber or copper), as otherwise we
1715 - * read the PHY capabilities from the wrong page.
1716 - */
1717 - phy_lock_mdio_bus(phydev);
1718 - ret = at803x_write_page(phydev,
1719 - priv->is_fiber ? AT803X_PAGE_FIBER :
1720 - AT803X_PAGE_COPPER);
1721 - phy_unlock_mdio_bus(phydev);
1722 - if (ret)
1723 - return ret;
1724 -
1725 - ret = at8031_pll_config(phydev);
1726 - if (ret < 0)
1727 - return ret;
1728 -
1729 - return at803x_config_init(phydev);
1730 -}
1731 -
1732 -static int at8031_set_wol(struct phy_device *phydev,
1733 - struct ethtool_wolinfo *wol)
1734 -{
1735 - int ret;
1736 -
1737 - /* First setup MAC address and enable WOL interrupt */
1738 - ret = at803x_set_wol(phydev, wol);
1739 - if (ret)
1740 - return ret;
1741 -
1742 - if (wol->wolopts & WAKE_MAGIC)
1743 - /* Enable WOL function for 1588 */
1744 - ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
1745 - AT803X_PHY_MMD3_WOL_CTRL,
1746 - 0, AT803X_WOL_EN);
1747 - else
1748 - /* Disable WoL function for 1588 */
1749 - ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
1750 - AT803X_PHY_MMD3_WOL_CTRL,
1751 - AT803X_WOL_EN, 0);
1752 -
1753 - return ret;
1754 -}
1755 -
1756 -static int at8031_config_intr(struct phy_device *phydev)
1757 -{
1758 - struct at803x_priv *priv = phydev->priv;
1759 - int err, value = 0;
1760 -
1761 - if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
1762 - priv->is_fiber) {
1763 - /* Clear any pending interrupts */
1764 - err = at803x_ack_interrupt(phydev);
1765 - if (err)
1766 - return err;
1767 -
1768 - value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
1769 - value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
1770 -
1771 - err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);
1772 - if (err)
1773 - return err;
1774 - }
1775 -
1776 - return at803x_config_intr(phydev);
1777 -}
1778 -
1779 -/* AR8031 and AR8033 share the same read status logic */
1780 -static int at8031_read_status(struct phy_device *phydev)
1781 -{
1782 - struct at803x_priv *priv = phydev->priv;
1783 -
1784 - if (priv->is_1000basex)
1785 - return genphy_c37_read_status(phydev);
1786 -
1787 - return at803x_read_status(phydev);
1788 -}
1789 -
1790 -/* AR8031 and AR8035 share the same cable test get status reg */
1791 -static int at8031_cable_test_get_status(struct phy_device *phydev,
1792 - bool *finished)
1793 -{
1794 - return at803x_cable_test_get_status(phydev, finished, 0xf);
1795 -}
1796 -
1797 -/* AR8031 and AR8035 share the same cable test start logic */
1798 -static int at8031_cable_test_start(struct phy_device *phydev)
1799 -{
1800 - at803x_cable_test_autoneg(phydev);
1801 - phy_write(phydev, MII_CTRL1000, 0);
1802 - /* we do all the (time consuming) work later */
1803 - return 0;
1804 -}
1805 -
1806 -/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
1807 -static int at8032_cable_test_get_status(struct phy_device *phydev,
1808 - bool *finished)
1809 -{
1810 - return at803x_cable_test_get_status(phydev, finished, 0x3);
1811 -}
1812 -
1813 -static int at8035_parse_dt(struct phy_device *phydev)
1814 -{
1815 - struct at803x_priv *priv = phydev->priv;
1816 -
1817 - /* Mask is set by the generic at803x_parse_dt
1818 - * if property is set. Assume property is set
1819 - * with the mask not zero.
1820 - */
1821 - if (priv->clk_25m_mask) {
1822 - /* Fixup for the AR8030/AR8035. This chip has another mask and
1823 - * doesn't support the DSP reference. Eg. the lowest bit of the
1824 - * mask. The upper two bits select the same frequencies. Mask
1825 - * the lowest bit here.
1826 - *
1827 - * Warning:
1828 - * There was no datasheet for the AR8030 available so this is
1829 - * just a guess. But the AR8035 is listed as pin compatible
1830 - * to the AR8030 so there might be a good chance it works on
1831 - * the AR8030 too.
1832 - */
1833 - priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
1834 - priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
1835 - }
1836 -
1837 - return 0;
1838 -}
1839 -
1840 -/* AR8030 and AR8035 shared the same special mask for clk_25m */
1841 -static int at8035_probe(struct phy_device *phydev)
1842 -{
1843 - int ret;
1844 -
1845 - ret = at803x_probe(phydev);
1846 - if (ret)
1847 - return ret;
1848 -
1849 - return at8035_parse_dt(phydev);
1850 -}
1851 -
1852 -static int qca83xx_config_init(struct phy_device *phydev)
1853 -{
1854 - u8 switch_revision;
1855 -
1856 - switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
1857 -
1858 - switch (switch_revision) {
1859 - case 1:
1860 - /* For 100M waveform */
1861 - at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
1862 - /* Turn on Gigabit clock */
1863 - at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
1864 - break;
1865 -
1866 - case 2:
1867 - phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
1868 - fallthrough;
1869 - case 4:
1870 - phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
1871 - at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
1872 - at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
1873 - at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
1874 - break;
1875 - }
1876 -
1877 - /* Following original QCA sourcecode set port to prefer master */
1878 - phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
1879 -
1880 - return 0;
1881 -}
1882 -
1883 -static int qca8327_config_init(struct phy_device *phydev)
1884 -{
1885 - /* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
1886 - * Disable on init and enable only with 100m speed following
1887 - * qca original source code.
1888 - */
1889 - at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1890 - QCA8327_DEBUG_MANU_CTRL_EN, 0);
1891 -
1892 - return qca83xx_config_init(phydev);
1893 -}
1894 -
1895 -static void qca83xx_link_change_notify(struct phy_device *phydev)
1896 -{
1897 - /* Set DAC Amplitude adjustment to +6% for 100m on link running */
1898 - if (phydev->state == PHY_RUNNING) {
1899 - if (phydev->speed == SPEED_100)
1900 - at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1901 - QCA8327_DEBUG_MANU_CTRL_EN,
1902 - QCA8327_DEBUG_MANU_CTRL_EN);
1903 - } else {
1904 - /* Reset DAC Amplitude adjustment */
1905 - at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
1906 - QCA8327_DEBUG_MANU_CTRL_EN, 0);
1907 - }
1908 -}
1909 -
1910 -static int qca83xx_resume(struct phy_device *phydev)
1911 -{
1912 - int ret, val;
1913 -
1914 - /* Skip reset if not suspended */
1915 - if (!phydev->suspended)
1916 - return 0;
1917 -
1918 - /* Reinit the port, reset values set by suspend */
1919 - qca83xx_config_init(phydev);
1920 -
1921 - /* Reset the port on port resume */
1922 - phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
1923 -
1924 - /* On resume from suspend the switch execute a reset and
1925 - * restart auto-negotiation. Wait for reset to complete.
1926 - */
1927 - ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
1928 - 50000, 600000, true);
1929 - if (ret)
1930 - return ret;
1931 -
1932 - usleep_range(1000, 2000);
1933 -
1934 - return 0;
1935 -}
1936 -
1937 -static int qca83xx_suspend(struct phy_device *phydev)
1938 -{
1939 - at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
1940 - AT803X_DEBUG_GATE_CLK_IN1000, 0);
1941 -
1942 - at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
1943 - AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
1944 - AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
1945 -
1946 - return 0;
1947 -}
1948 -
1949 -static int qca8337_suspend(struct phy_device *phydev)
1950 -{
1951 - /* Only QCA8337 support actual suspend. */
1952 - genphy_suspend(phydev);
1953 -
1954 - return qca83xx_suspend(phydev);
1955 -}
1956 -
1957 -static int qca8327_suspend(struct phy_device *phydev)
1958 -{
1959 - u16 mask = 0;
1960 -
1961 - /* QCA8327 cause port unreliability when phy suspend
1962 - * is set.
1963 - */
1964 - mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
1965 - phy_modify(phydev, MII_BMCR, mask, 0);
1966 -
1967 - return qca83xx_suspend(phydev);
1968 -}
1969 -
1970 -static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
1971 -{
1972 - int ret;
1973 -
1974 - /* Enable fast retrain */
1975 - ret = genphy_c45_fast_retrain(phydev, true);
1976 - if (ret)
1977 - return ret;
1978 -
1979 - phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
1980 - QCA808X_TOP_OPTION1_DATA);
1981 - phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
1982 - QCA808X_MSE_THRESHOLD_20DB_VALUE);
1983 - phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
1984 - QCA808X_MSE_THRESHOLD_17DB_VALUE);
1985 - phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
1986 - QCA808X_MSE_THRESHOLD_27DB_VALUE);
1987 - phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
1988 - QCA808X_MSE_THRESHOLD_28DB_VALUE);
1989 - phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
1990 - QCA808X_MMD3_DEBUG_1_VALUE);
1991 - phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
1992 - QCA808X_MMD3_DEBUG_4_VALUE);
1993 - phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
1994 - QCA808X_MMD3_DEBUG_5_VALUE);
1995 - phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
1996 - QCA808X_MMD3_DEBUG_3_VALUE);
1997 - phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
1998 - QCA808X_MMD3_DEBUG_6_VALUE);
1999 - phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
2000 - QCA808X_MMD3_DEBUG_2_VALUE);
2001 -
2002 - return 0;
2003 -}
2004 -
2005 -static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
2006 -{
2007 - u16 seed_value;
2008 -
2009 - if (!enable)
2010 - return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
2011 - QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
2012 -
2013 - seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE);
2014 - return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
2015 - QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
2016 - FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
2017 - QCA808X_MASTER_SLAVE_SEED_ENABLE);
2018 -}
2019 -
2020 -static bool qca808x_is_prefer_master(struct phy_device *phydev)
2021 -{
2022 - return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
2023 - (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
2024 -}
2025 -
2026 -static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
2027 -{
2028 - return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
2029 -}
2030 -
2031 -static int qca808x_config_init(struct phy_device *phydev)
2032 -{
2033 - int ret;
2034 -
2035 - /* Active adc&vga on 802.3az for the link 1000M and 100M */
2036 - ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
2037 - QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
2038 - if (ret)
2039 - return ret;
2040 -
2041 - /* Adjust the threshold on 802.3az for the link 1000M */
2042 - ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
2043 - QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
2044 - QCA808X_MMD3_AZ_TRAINING_VAL);
2045 - if (ret)
2046 - return ret;
2047 -
2048 - if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
2049 - /* Config the fast retrain for the link 2500M */
2050 - ret = qca808x_phy_fast_retrain_config(phydev);
2051 - if (ret)
2052 - return ret;
2053 -
2054 - ret = genphy_read_master_slave(phydev);
2055 - if (ret < 0)
2056 - return ret;
2057 -
2058 - if (!qca808x_is_prefer_master(phydev)) {
2059 - /* Enable seed and configure lower ramdom seed to make phy
2060 - * linked as slave mode.
2061 - */
2062 - ret = qca808x_phy_ms_seed_enable(phydev, true);
2063 - if (ret)
2064 - return ret;
2065 - }
2066 - }
2067 -
2068 - /* Configure adc threshold as 100mv for the link 10M */
2069 - return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
2070 - QCA808X_ADC_THRESHOLD_MASK,
2071 - QCA808X_ADC_THRESHOLD_100MV);
2072 -}
2073 -
2074 -static int qca808x_read_status(struct phy_device *phydev)
2075 -{
2076 - struct at803x_ss_mask ss_mask = { 0 };
2077 - int ret;
2078 -
2079 - ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
2080 - if (ret < 0)
2081 - return ret;
2082 -
2083 - linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
2084 - ret & MDIO_AN_10GBT_STAT_LP2_5G);
2085 -
2086 - ret = genphy_read_status(phydev);
2087 - if (ret)
2088 - return ret;
2089 -
2090 - /* qca8081 takes the different bits for speed value from at803x */
2091 - ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
2092 - ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
2093 - ret = at803x_read_specific_status(phydev, ss_mask);
2094 - if (ret < 0)
2095 - return ret;
2096 -
2097 - if (phydev->link) {
2098 - if (phydev->speed == SPEED_2500)
2099 - phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
2100 - else
2101 - phydev->interface = PHY_INTERFACE_MODE_SGMII;
2102 - } else {
2103 - /* generate seed as a lower random value to make PHY linked as SLAVE easily,
2104 - * except for master/slave configuration fault detected or the master mode
2105 - * preferred.
2106 - *
2107 - * the reason for not putting this code into the function link_change_notify is
2108 - * the corner case where the link partner is also the qca8081 PHY and the seed
2109 - * value is configured as the same value, the link can't be up and no link change
2110 - * occurs.
2111 - */
2112 - if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
2113 - if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
2114 - qca808x_is_prefer_master(phydev)) {
2115 - qca808x_phy_ms_seed_enable(phydev, false);
2116 - } else {
2117 - qca808x_phy_ms_seed_enable(phydev, true);
2118 - }
2119 - }
2120 - }
2121 -
2122 - return 0;
2123 -}
2124 -
2125 -static int qca808x_soft_reset(struct phy_device *phydev)
2126 -{
2127 - int ret;
2128 -
2129 - ret = genphy_soft_reset(phydev);
2130 - if (ret < 0)
2131 - return ret;
2132 -
2133 - if (qca808x_has_fast_retrain_or_slave_seed(phydev))
2134 - ret = qca808x_phy_ms_seed_enable(phydev, true);
2135 -
2136 - return ret;
2137 -}
2138 -
2139 -static bool qca808x_cdt_fault_length_valid(int cdt_code)
2140 -{
2141 - switch (cdt_code) {
2142 - case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
2143 - case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
2144 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
2145 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
2146 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
2147 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
2148 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
2149 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
2150 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
2151 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
2152 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
2153 - return true;
2154 - default:
2155 - return false;
2156 - }
2157 -}
2158 -
2159 -static int qca808x_cable_test_result_trans(int cdt_code)
2160 -{
2161 - switch (cdt_code) {
2162 - case QCA808X_CDT_STATUS_STAT_NORMAL:
2163 - return ETHTOOL_A_CABLE_RESULT_CODE_OK;
2164 - case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
2165 - return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
2166 - case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
2167 - return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
2168 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
2169 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
2170 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
2171 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
2172 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
2173 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
2174 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
2175 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
2176 - case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
2177 - return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
2178 - case QCA808X_CDT_STATUS_STAT_FAIL:
2179 - default:
2180 - return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
2181 - }
2182 -}
2183 -
2184 -static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
2185 - int result)
2186 -{
2187 - int val;
2188 - u32 cdt_length_reg = 0;
2189 -
2190 - switch (pair) {
2191 - case ETHTOOL_A_CABLE_PAIR_A:
2192 - cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
2193 - break;
2194 - case ETHTOOL_A_CABLE_PAIR_B:
2195 - cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
2196 - break;
2197 - case ETHTOOL_A_CABLE_PAIR_C:
2198 - cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
2199 - break;
2200 - case ETHTOOL_A_CABLE_PAIR_D:
2201 - cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
2202 - break;
2203 - default:
2204 - return -EINVAL;
2205 - }
2206 -
2207 - val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
2208 - if (val < 0)
2209 - return val;
2210 -
2211 - if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
2212 - val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
2213 - else
2214 - val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
2215 -
2216 - return at803x_cdt_fault_length(val);
2217 -}
2218 -
2219 -static int qca808x_cable_test_start(struct phy_device *phydev)
2220 -{
2221 - int ret;
2222 -
2223 - /* perform CDT with the following configs:
2224 - * 1. disable hibernation.
2225 - * 2. force PHY working in MDI mode.
2226 - * 3. for PHY working in 1000BaseT.
2227 - * 4. configure the threshold.
2228 - */
2229 -
2230 - ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
2231 - if (ret < 0)
2232 - return ret;
2233 -
2234 - ret = at803x_config_mdix(phydev, ETH_TP_MDI);
2235 - if (ret < 0)
2236 - return ret;
2237 -
2238 - /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
2239 - phydev->duplex = DUPLEX_FULL;
2240 - phydev->speed = SPEED_1000;
2241 - ret = genphy_c45_pma_setup_forced(phydev);
2242 - if (ret < 0)
2243 - return ret;
2244 -
2245 - ret = genphy_setup_forced(phydev);
2246 - if (ret < 0)
2247 - return ret;
2248 -
2249 - /* configure the thresholds for open, short, pair ok test */
2250 - phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
2251 - phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
2252 - phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
2253 - phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
2254 - phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
2255 - phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
2256 -
2257 - return 0;
2258 -}
2259 -
2260 -static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
2261 - u16 status)
2262 -{
2263 - int length, result;
2264 - u16 pair_code;
2265 -
2266 - switch (pair) {
2267 - case ETHTOOL_A_CABLE_PAIR_A:
2268 - pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
2269 - break;
2270 - case ETHTOOL_A_CABLE_PAIR_B:
2271 - pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
2272 - break;
2273 - case ETHTOOL_A_CABLE_PAIR_C:
2274 - pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
2275 - break;
2276 - case ETHTOOL_A_CABLE_PAIR_D:
2277 - pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
2278 - break;
2279 - default:
2280 - return -EINVAL;
2281 - }
2282 -
2283 - result = qca808x_cable_test_result_trans(pair_code);
2284 - ethnl_cable_test_result(phydev, pair, result);
2285 -
2286 - if (qca808x_cdt_fault_length_valid(pair_code)) {
2287 - length = qca808x_cdt_fault_length(phydev, pair, result);
2288 - ethnl_cable_test_fault_length(phydev, pair, length);
2289 - }
2290 -
2291 - return 0;
2292 -}
2293 -
2294 -static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
2295 -{
2296 - int ret, val;
2297 -
2298 - *finished = false;
2299 -
2300 - val = QCA808X_CDT_ENABLE_TEST |
2301 - QCA808X_CDT_LENGTH_UNIT;
2302 - ret = at803x_cdt_start(phydev, val);
2303 - if (ret)
2304 - return ret;
2305 -
2306 - ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
2307 - if (ret)
2308 - return ret;
2309 -
2310 - val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
2311 - if (val < 0)
2312 - return val;
2313 -
2314 - ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
2315 - if (ret)
2316 - return ret;
2317 -
2318 - ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
2319 - if (ret)
2320 - return ret;
2321 -
2322 - ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
2323 - if (ret)
2324 - return ret;
2325 -
2326 - ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
2327 - if (ret)
2328 - return ret;
2329 -
2330 - *finished = true;
2331 -
2332 - return 0;
2333 -}
2334 -
2335 -static int qca808x_get_features(struct phy_device *phydev)
2336 -{
2337 - int ret;
2338 -
2339 - ret = genphy_c45_pma_read_abilities(phydev);
2340 - if (ret)
2341 - return ret;
2342 -
2343 - /* The autoneg ability is not existed in bit3 of MMD7.1,
2344 - * but it is supported by qca808x PHY, so we add it here
2345 - * manually.
2346 - */
2347 - linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
2348 -
2349 - /* As for the qca8081 1G version chip, the 2500baseT ability is also
2350 - * existed in the bit0 of MMD1.21, we need to remove it manually if
2351 - * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
2352 - */
2353 - ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
2354 - if (ret < 0)
2355 - return ret;
2356 -
2357 - if (QCA808X_PHY_CHIP_TYPE_1G & ret)
2358 - linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
2359 -
2360 - return 0;
2361 -}
2362 -
2363 -static int qca808x_config_aneg(struct phy_device *phydev)
2364 -{
2365 - int phy_ctrl = 0;
2366 - int ret;
2367 -
2368 - ret = at803x_prepare_config_aneg(phydev);
2369 - if (ret)
2370 - return ret;
2371 -
2372 - /* The reg MII_BMCR also needs to be configured for force mode, the
2373 - * genphy_config_aneg is also needed.
2374 - */
2375 - if (phydev->autoneg == AUTONEG_DISABLE)
2376 - genphy_c45_pma_setup_forced(phydev);
2377 -
2378 - if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
2379 - phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
2380 -
2381 - ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
2382 - MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
2383 - if (ret < 0)
2384 - return ret;
2385 -
2386 - return __genphy_config_aneg(phydev, ret);
2387 -}
2388 -
2389 -static void qca808x_link_change_notify(struct phy_device *phydev)
2390 -{
2391 - /* Assert interface sgmii fifo on link down, deassert it on link up,
2392 - * the interface device address is always phy address added by 1.
2393 - */
2394 - mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
2395 - MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
2396 - QCA8081_PHY_FIFO_RSTN,
2397 - phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
2398 -}
2399 -
2400 -static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
2401 - u16 *offload_trigger)
2402 -{
2403 - /* Parsing specific to netdev trigger */
2404 - if (test_bit(TRIGGER_NETDEV_TX, &rules))
2405 - *offload_trigger |= QCA808X_LED_TX_BLINK;
2406 - if (test_bit(TRIGGER_NETDEV_RX, &rules))
2407 - *offload_trigger |= QCA808X_LED_RX_BLINK;
2408 - if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
2409 - *offload_trigger |= QCA808X_LED_SPEED10_ON;
2410 - if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
2411 - *offload_trigger |= QCA808X_LED_SPEED100_ON;
2412 - if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
2413 - *offload_trigger |= QCA808X_LED_SPEED1000_ON;
2414 - if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
2415 - *offload_trigger |= QCA808X_LED_SPEED2500_ON;
2416 - if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
2417 - *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
2418 - if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
2419 - *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
2420 -
2421 - if (rules && !*offload_trigger)
2422 - return -EOPNOTSUPP;
2423 -
2424 - /* Enable BLINK_CHECK_BYPASS by default to make the LED
2425 - * blink even with duplex or speed mode not enabled.
2426 - */
2427 - *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
2428 -
2429 - return 0;
2430 -}
2431 -
2432 -static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
2433 -{
2434 - u16 reg;
2435 -
2436 - if (index > 2)
2437 - return -EINVAL;
2438 -
2439 - reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
2440 -
2441 - return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
2442 - QCA808X_LED_FORCE_EN);
2443 -}
2444 -
2445 -static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
2446 - unsigned long rules)
2447 -{
2448 - u16 offload_trigger = 0;
2449 -
2450 - if (index > 2)
2451 - return -EINVAL;
2452 -
2453 - return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
2454 -}
2455 -
2456 -static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
2457 - unsigned long rules)
2458 -{
2459 - u16 reg, offload_trigger = 0;
2460 - int ret;
2461 -
2462 - if (index > 2)
2463 - return -EINVAL;
2464 -
2465 - reg = QCA808X_MMD7_LED_CTRL(index);
2466 -
2467 - ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
2468 - if (ret)
2469 - return ret;
2470 -
2471 - ret = qca808x_led_hw_control_enable(phydev, index);
2472 - if (ret)
2473 - return ret;
2474 -
2475 - return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
2476 - QCA808X_LED_PATTERN_MASK,
2477 - offload_trigger);
2478 -}
2479 -
2480 -static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
2481 -{
2482 - u16 reg;
2483 - int val;
2484 -
2485 - if (index > 2)
2486 - return false;
2487 -
2488 - reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
2489 -
2490 - val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
2491 -
2492 - return !(val & QCA808X_LED_FORCE_EN);
2493 -}
2494 -
2495 -static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
2496 - unsigned long *rules)
2497 -{
2498 - u16 reg;
2499 - int val;
2500 -
2501 - if (index > 2)
2502 - return -EINVAL;
2503 -
2504 - /* Check if we have hw control enabled */
2505 - if (qca808x_led_hw_control_status(phydev, index))
2506 - return -EINVAL;
2507 -
2508 - reg = QCA808X_MMD7_LED_CTRL(index);
2509 -
2510 - val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
2511 - if (val & QCA808X_LED_TX_BLINK)
2512 - set_bit(TRIGGER_NETDEV_TX, rules);
2513 - if (val & QCA808X_LED_RX_BLINK)
2514 - set_bit(TRIGGER_NETDEV_RX, rules);
2515 - if (val & QCA808X_LED_SPEED10_ON)
2516 - set_bit(TRIGGER_NETDEV_LINK_10, rules);
2517 - if (val & QCA808X_LED_SPEED100_ON)
2518 - set_bit(TRIGGER_NETDEV_LINK_100, rules);
2519 - if (val & QCA808X_LED_SPEED1000_ON)
2520 - set_bit(TRIGGER_NETDEV_LINK_1000, rules);
2521 - if (val & QCA808X_LED_SPEED2500_ON)
2522 - set_bit(TRIGGER_NETDEV_LINK_2500, rules);
2523 - if (val & QCA808X_LED_HALF_DUPLEX_ON)
2524 - set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
2525 - if (val & QCA808X_LED_FULL_DUPLEX_ON)
2526 - set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
2527 -
2528 - return 0;
2529 -}
2530 -
2531 -static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
2532 -{
2533 - u16 reg;
2534 -
2535 - if (index > 2)
2536 - return -EINVAL;
2537 -
2538 - reg = QCA808X_MMD7_LED_CTRL(index);
2539 -
2540 - return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
2541 - QCA808X_LED_PATTERN_MASK);
2542 -}
2543 -
2544 -static int qca808x_led_brightness_set(struct phy_device *phydev,
2545 - u8 index, enum led_brightness value)
2546 -{
2547 - u16 reg;
2548 - int ret;
2549 -
2550 - if (index > 2)
2551 - return -EINVAL;
2552 -
2553 - if (!value) {
2554 - ret = qca808x_led_hw_control_reset(phydev, index);
2555 - if (ret)
2556 - return ret;
2557 - }
2558 -
2559 - reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
2560 -
2561 - return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
2562 - QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
2563 - QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
2564 - QCA808X_LED_FORCE_OFF);
2565 -}
2566 -
2567 -static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
2568 - unsigned long *delay_on,
2569 - unsigned long *delay_off)
2570 -{
2571 - int ret;
2572 - u16 reg;
2573 -
2574 - if (index > 2)
2575 - return -EINVAL;
2576 -
2577 - reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
2578 -
2579 - /* Set blink to 50% off, 50% on at 4Hz by default */
2580 - ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
2581 - QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
2582 - QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
2583 - if (ret)
2584 - return ret;
2585 -
2586 - /* We use BLINK_1 for normal blinking */
2587 - ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
2588 - QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
2589 - QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
2590 - if (ret)
2591 - return ret;
2592 -
2593 - /* We set blink to 4Hz, aka 250ms */
2594 - *delay_on = 250 / 2;
2595 - *delay_off = 250 / 2;
2596 -
2597 - return 0;
2598 -}
2599 -
2600 -static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
2601 - unsigned long modes)
2602 -{
2603 - struct at803x_priv *priv = phydev->priv;
2604 - bool active_low = false;
2605 - u32 mode;
2606 -
2607 - for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
2608 - switch (mode) {
2609 - case PHY_LED_ACTIVE_LOW:
2610 - active_low = true;
2611 - break;
2612 - default:
2613 - return -EINVAL;
2614 - }
2615 - }
2616 -
2617 - /* PHY polarity is global and can't be set per LED.
2618 - * To detect this, check if last requested polarity mode
2619 - * match the new one.
2620 - */
2621 - if (priv->led_polarity_mode >= 0 &&
2622 - priv->led_polarity_mode != active_low) {
2623 - phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
2624 - return -EINVAL;
2625 - }
2626 -
2627 - /* Save the last PHY polarity mode */
2628 - priv->led_polarity_mode = active_low;
2629 -
2630 - return phy_modify_mmd(phydev, MDIO_MMD_AN,
2631 - QCA808X_MMD7_LED_POLARITY_CTRL,
2632 - QCA808X_LED_ACTIVE_HIGH,
2633 - active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
2634 -}
2635 -
2636 -static struct phy_driver at803x_driver[] = {
2637 -{
2638 - /* Qualcomm Atheros AR8035 */
2639 - PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
2640 - .name = "Qualcomm Atheros AR8035",
2641 - .flags = PHY_POLL_CABLE_TEST,
2642 - .probe = at8035_probe,
2643 - .config_aneg = at803x_config_aneg,
2644 - .config_init = at803x_config_init,
2645 - .soft_reset = genphy_soft_reset,
2646 - .set_wol = at803x_set_wol,
2647 - .get_wol = at803x_get_wol,
2648 - .suspend = at803x_suspend,
2649 - .resume = at803x_resume,
2650 - /* PHY_GBIT_FEATURES */
2651 - .read_status = at803x_read_status,
2652 - .config_intr = at803x_config_intr,
2653 - .handle_interrupt = at803x_handle_interrupt,
2654 - .get_tunable = at803x_get_tunable,
2655 - .set_tunable = at803x_set_tunable,
2656 - .cable_test_start = at8031_cable_test_start,
2657 - .cable_test_get_status = at8031_cable_test_get_status,
2658 -}, {
2659 - /* Qualcomm Atheros AR8030 */
2660 - .phy_id = ATH8030_PHY_ID,
2661 - .name = "Qualcomm Atheros AR8030",
2662 - .phy_id_mask = AT8030_PHY_ID_MASK,
2663 - .probe = at8035_probe,
2664 - .config_init = at803x_config_init,
2665 - .link_change_notify = at803x_link_change_notify,
2666 - .set_wol = at803x_set_wol,
2667 - .get_wol = at803x_get_wol,
2668 - .suspend = at803x_suspend,
2669 - .resume = at803x_resume,
2670 - /* PHY_BASIC_FEATURES */
2671 - .config_intr = at803x_config_intr,
2672 - .handle_interrupt = at803x_handle_interrupt,
2673 -}, {
2674 - /* Qualcomm Atheros AR8031/AR8033 */
2675 - PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
2676 - .name = "Qualcomm Atheros AR8031/AR8033",
2677 - .flags = PHY_POLL_CABLE_TEST,
2678 - .probe = at8031_probe,
2679 - .config_init = at8031_config_init,
2680 - .config_aneg = at803x_config_aneg,
2681 - .soft_reset = genphy_soft_reset,
2682 - .set_wol = at8031_set_wol,
2683 - .get_wol = at803x_get_wol,
2684 - .suspend = at803x_suspend,
2685 - .resume = at803x_resume,
2686 - .read_page = at803x_read_page,
2687 - .write_page = at803x_write_page,
2688 - .get_features = at803x_get_features,
2689 - .read_status = at8031_read_status,
2690 - .config_intr = at8031_config_intr,
2691 - .handle_interrupt = at803x_handle_interrupt,
2692 - .get_tunable = at803x_get_tunable,
2693 - .set_tunable = at803x_set_tunable,
2694 - .cable_test_start = at8031_cable_test_start,
2695 - .cable_test_get_status = at8031_cable_test_get_status,
2696 -}, {
2697 - /* Qualcomm Atheros AR8032 */
2698 - PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
2699 - .name = "Qualcomm Atheros AR8032",
2700 - .probe = at803x_probe,
2701 - .flags = PHY_POLL_CABLE_TEST,
2702 - .config_init = at803x_config_init,
2703 - .link_change_notify = at803x_link_change_notify,
2704 - .suspend = at803x_suspend,
2705 - .resume = at803x_resume,
2706 - /* PHY_BASIC_FEATURES */
2707 - .config_intr = at803x_config_intr,
2708 - .handle_interrupt = at803x_handle_interrupt,
2709 - .cable_test_start = at803x_cable_test_start,
2710 - .cable_test_get_status = at8032_cable_test_get_status,
2711 -}, {
2712 - /* ATHEROS AR9331 */
2713 - PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
2714 - .name = "Qualcomm Atheros AR9331 built-in PHY",
2715 - .probe = at803x_probe,
2716 - .suspend = at803x_suspend,
2717 - .resume = at803x_resume,
2718 - .flags = PHY_POLL_CABLE_TEST,
2719 - /* PHY_BASIC_FEATURES */
2720 - .config_intr = at803x_config_intr,
2721 - .handle_interrupt = at803x_handle_interrupt,
2722 - .cable_test_start = at803x_cable_test_start,
2723 - .cable_test_get_status = at8032_cable_test_get_status,
2724 - .read_status = at803x_read_status,
2725 - .soft_reset = genphy_soft_reset,
2726 - .config_aneg = at803x_config_aneg,
2727 -}, {
2728 - /* Qualcomm Atheros QCA9561 */
2729 - PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
2730 - .name = "Qualcomm Atheros QCA9561 built-in PHY",
2731 - .probe = at803x_probe,
2732 - .suspend = at803x_suspend,
2733 - .resume = at803x_resume,
2734 - .flags = PHY_POLL_CABLE_TEST,
2735 - /* PHY_BASIC_FEATURES */
2736 - .config_intr = at803x_config_intr,
2737 - .handle_interrupt = at803x_handle_interrupt,
2738 - .cable_test_start = at803x_cable_test_start,
2739 - .cable_test_get_status = at8032_cable_test_get_status,
2740 - .read_status = at803x_read_status,
2741 - .soft_reset = genphy_soft_reset,
2742 - .config_aneg = at803x_config_aneg,
2743 -}, {
2744 - /* QCA8337 */
2745 - .phy_id = QCA8337_PHY_ID,
2746 - .phy_id_mask = QCA8K_PHY_ID_MASK,
2747 - .name = "Qualcomm Atheros 8337 internal PHY",
2748 - /* PHY_GBIT_FEATURES */
2749 - .probe = at803x_probe,
2750 - .flags = PHY_IS_INTERNAL,
2751 - .config_init = qca83xx_config_init,
2752 - .soft_reset = genphy_soft_reset,
2753 - .get_sset_count = qca83xx_get_sset_count,
2754 - .get_strings = qca83xx_get_strings,
2755 - .get_stats = qca83xx_get_stats,
2756 - .suspend = qca8337_suspend,
2757 - .resume = qca83xx_resume,
2758 -}, {
2759 - /* QCA8327-A from switch QCA8327-AL1A */
2760 - .phy_id = QCA8327_A_PHY_ID,
2761 - .phy_id_mask = QCA8K_PHY_ID_MASK,
2762 - .name = "Qualcomm Atheros 8327-A internal PHY",
2763 - /* PHY_GBIT_FEATURES */
2764 - .link_change_notify = qca83xx_link_change_notify,
2765 - .probe = at803x_probe,
2766 - .flags = PHY_IS_INTERNAL,
2767 - .config_init = qca8327_config_init,
2768 - .soft_reset = genphy_soft_reset,
2769 - .get_sset_count = qca83xx_get_sset_count,
2770 - .get_strings = qca83xx_get_strings,
2771 - .get_stats = qca83xx_get_stats,
2772 - .suspend = qca8327_suspend,
2773 - .resume = qca83xx_resume,
2774 -}, {
2775 - /* QCA8327-B from switch QCA8327-BL1A */
2776 - .phy_id = QCA8327_B_PHY_ID,
2777 - .phy_id_mask = QCA8K_PHY_ID_MASK,
2778 - .name = "Qualcomm Atheros 8327-B internal PHY",
2779 - /* PHY_GBIT_FEATURES */
2780 - .link_change_notify = qca83xx_link_change_notify,
2781 - .probe = at803x_probe,
2782 - .flags = PHY_IS_INTERNAL,
2783 - .config_init = qca8327_config_init,
2784 - .soft_reset = genphy_soft_reset,
2785 - .get_sset_count = qca83xx_get_sset_count,
2786 - .get_strings = qca83xx_get_strings,
2787 - .get_stats = qca83xx_get_stats,
2788 - .suspend = qca8327_suspend,
2789 - .resume = qca83xx_resume,
2790 -}, {
2791 - /* Qualcomm QCA8081 */
2792 - PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
2793 - .name = "Qualcomm QCA8081",
2794 - .flags = PHY_POLL_CABLE_TEST,
2795 - .probe = at803x_probe,
2796 - .config_intr = at803x_config_intr,
2797 - .handle_interrupt = at803x_handle_interrupt,
2798 - .get_tunable = at803x_get_tunable,
2799 - .set_tunable = at803x_set_tunable,
2800 - .set_wol = at803x_set_wol,
2801 - .get_wol = at803x_get_wol,
2802 - .get_features = qca808x_get_features,
2803 - .config_aneg = qca808x_config_aneg,
2804 - .suspend = genphy_suspend,
2805 - .resume = genphy_resume,
2806 - .read_status = qca808x_read_status,
2807 - .config_init = qca808x_config_init,
2808 - .soft_reset = qca808x_soft_reset,
2809 - .cable_test_start = qca808x_cable_test_start,
2810 - .cable_test_get_status = qca808x_cable_test_get_status,
2811 - .link_change_notify = qca808x_link_change_notify,
2812 - .led_brightness_set = qca808x_led_brightness_set,
2813 - .led_blink_set = qca808x_led_blink_set,
2814 - .led_hw_is_supported = qca808x_led_hw_is_supported,
2815 - .led_hw_control_set = qca808x_led_hw_control_set,
2816 - .led_hw_control_get = qca808x_led_hw_control_get,
2817 - .led_polarity_set = qca808x_led_polarity_set,
2818 -}, };
2819 -
2820 -module_phy_driver(at803x_driver);
2821 -
2822 -static struct mdio_device_id __maybe_unused atheros_tbl[] = {
2823 - { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
2824 - { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
2825 - { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
2826 - { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
2827 - { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
2828 - { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
2829 - { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
2830 - { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
2831 - { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
2832 - { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
2833 - { }
2834 -};
2835 -
2836 -MODULE_DEVICE_TABLE(mdio, atheros_tbl);
2837 --- /dev/null
2838 +++ b/drivers/net/phy/qcom/at803x.c
2839 @@ -0,0 +1,2759 @@
2840 +// SPDX-License-Identifier: GPL-2.0+
2841 +/*
2842 + * drivers/net/phy/at803x.c
2843 + *
2844 + * Driver for Qualcomm Atheros AR803x PHY
2845 + *
2846 + * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
2847 + */
2848 +
2849 +#include <linux/phy.h>
2850 +#include <linux/module.h>
2851 +#include <linux/string.h>
2852 +#include <linux/netdevice.h>
2853 +#include <linux/etherdevice.h>
2854 +#include <linux/ethtool_netlink.h>
2855 +#include <linux/bitfield.h>
2856 +#include <linux/regulator/of_regulator.h>
2857 +#include <linux/regulator/driver.h>
2858 +#include <linux/regulator/consumer.h>
2859 +#include <linux/of.h>
2860 +#include <linux/phylink.h>
2861 +#include <linux/sfp.h>
2862 +#include <dt-bindings/net/qca-ar803x.h>
2863 +
2864 +#define AT803X_SPECIFIC_FUNCTION_CONTROL 0x10
2865 +#define AT803X_SFC_ASSERT_CRS BIT(11)
2866 +#define AT803X_SFC_FORCE_LINK BIT(10)
2867 +#define AT803X_SFC_MDI_CROSSOVER_MODE_M GENMASK(6, 5)
2868 +#define AT803X_SFC_AUTOMATIC_CROSSOVER 0x3
2869 +#define AT803X_SFC_MANUAL_MDIX 0x1
2870 +#define AT803X_SFC_MANUAL_MDI 0x0
2871 +#define AT803X_SFC_SQE_TEST BIT(2)
2872 +#define AT803X_SFC_POLARITY_REVERSAL BIT(1)
2873 +#define AT803X_SFC_DISABLE_JABBER BIT(0)
2874 +
2875 +#define AT803X_SPECIFIC_STATUS 0x11
2876 +#define AT803X_SS_SPEED_MASK GENMASK(15, 14)
2877 +#define AT803X_SS_SPEED_1000 2
2878 +#define AT803X_SS_SPEED_100 1
2879 +#define AT803X_SS_SPEED_10 0
2880 +#define AT803X_SS_DUPLEX BIT(13)
2881 +#define AT803X_SS_SPEED_DUPLEX_RESOLVED BIT(11)
2882 +#define AT803X_SS_MDIX BIT(6)
2883 +
2884 +#define QCA808X_SS_SPEED_MASK GENMASK(9, 7)
2885 +#define QCA808X_SS_SPEED_2500 4
2886 +
2887 +#define AT803X_INTR_ENABLE 0x12
2888 +#define AT803X_INTR_ENABLE_AUTONEG_ERR BIT(15)
2889 +#define AT803X_INTR_ENABLE_SPEED_CHANGED BIT(14)
2890 +#define AT803X_INTR_ENABLE_DUPLEX_CHANGED BIT(13)
2891 +#define AT803X_INTR_ENABLE_PAGE_RECEIVED BIT(12)
2892 +#define AT803X_INTR_ENABLE_LINK_FAIL BIT(11)
2893 +#define AT803X_INTR_ENABLE_LINK_SUCCESS BIT(10)
2894 +#define AT803X_INTR_ENABLE_LINK_FAIL_BX BIT(8)
2895 +#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX BIT(7)
2896 +#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE BIT(5)
2897 +#define AT803X_INTR_ENABLE_POLARITY_CHANGED BIT(1)
2898 +#define AT803X_INTR_ENABLE_WOL BIT(0)
2899 +
2900 +#define AT803X_INTR_STATUS 0x13
2901 +
2902 +#define AT803X_SMART_SPEED 0x14
2903 +#define AT803X_SMART_SPEED_ENABLE BIT(5)
2904 +#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK GENMASK(4, 2)
2905 +#define AT803X_SMART_SPEED_BYPASS_TIMER BIT(1)
2906 +#define AT803X_CDT 0x16
2907 +#define AT803X_CDT_MDI_PAIR_MASK GENMASK(9, 8)
2908 +#define AT803X_CDT_ENABLE_TEST BIT(0)
2909 +#define AT803X_CDT_STATUS 0x1c
2910 +#define AT803X_CDT_STATUS_STAT_NORMAL 0
2911 +#define AT803X_CDT_STATUS_STAT_SHORT 1
2912 +#define AT803X_CDT_STATUS_STAT_OPEN 2
2913 +#define AT803X_CDT_STATUS_STAT_FAIL 3
2914 +#define AT803X_CDT_STATUS_STAT_MASK GENMASK(9, 8)
2915 +#define AT803X_CDT_STATUS_DELTA_TIME_MASK GENMASK(7, 0)
2916 +#define AT803X_LED_CONTROL 0x18
2917 +
2918 +#define AT803X_PHY_MMD3_WOL_CTRL 0x8012
2919 +#define AT803X_WOL_EN BIT(5)
2920 +#define AT803X_LOC_MAC_ADDR_0_15_OFFSET 0x804C
2921 +#define AT803X_LOC_MAC_ADDR_16_31_OFFSET 0x804B
2922 +#define AT803X_LOC_MAC_ADDR_32_47_OFFSET 0x804A
2923 +#define AT803X_REG_CHIP_CONFIG 0x1f
2924 +#define AT803X_BT_BX_REG_SEL 0x8000
2925 +
2926 +#define AT803X_DEBUG_ADDR 0x1D
2927 +#define AT803X_DEBUG_DATA 0x1E
2928 +
2929 +#define AT803X_MODE_CFG_MASK 0x0F
2930 +#define AT803X_MODE_CFG_BASET_RGMII 0x00
2931 +#define AT803X_MODE_CFG_BASET_SGMII 0x01
2932 +#define AT803X_MODE_CFG_BX1000_RGMII_50OHM 0x02
2933 +#define AT803X_MODE_CFG_BX1000_RGMII_75OHM 0x03
2934 +#define AT803X_MODE_CFG_BX1000_CONV_50OHM 0x04
2935 +#define AT803X_MODE_CFG_BX1000_CONV_75OHM 0x05
2936 +#define AT803X_MODE_CFG_FX100_RGMII_50OHM 0x06
2937 +#define AT803X_MODE_CFG_FX100_CONV_50OHM 0x07
2938 +#define AT803X_MODE_CFG_RGMII_AUTO_MDET 0x0B
2939 +#define AT803X_MODE_CFG_FX100_RGMII_75OHM 0x0E
2940 +#define AT803X_MODE_CFG_FX100_CONV_75OHM 0x0F
2941 +
2942 +#define AT803X_PSSR 0x11 /*PHY-Specific Status Register*/
2943 +#define AT803X_PSSR_MR_AN_COMPLETE 0x0200
2944 +
2945 +#define AT803X_DEBUG_ANALOG_TEST_CTRL 0x00
2946 +#define QCA8327_DEBUG_MANU_CTRL_EN BIT(2)
2947 +#define QCA8337_DEBUG_MANU_CTRL_EN GENMASK(3, 2)
2948 +#define AT803X_DEBUG_RX_CLK_DLY_EN BIT(15)
2949 +
2950 +#define AT803X_DEBUG_SYSTEM_CTRL_MODE 0x05
2951 +#define AT803X_DEBUG_TX_CLK_DLY_EN BIT(8)
2952 +
2953 +#define AT803X_DEBUG_REG_HIB_CTRL 0x0b
2954 +#define AT803X_DEBUG_HIB_CTRL_SEL_RST_80U BIT(10)
2955 +#define AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE BIT(13)
2956 +#define AT803X_DEBUG_HIB_CTRL_PS_HIB_EN BIT(15)
2957 +
2958 +#define AT803X_DEBUG_REG_3C 0x3C
2959 +
2960 +#define AT803X_DEBUG_REG_GREEN 0x3D
2961 +#define AT803X_DEBUG_GATE_CLK_IN1000 BIT(6)
2962 +
2963 +#define AT803X_DEBUG_REG_1F 0x1F
2964 +#define AT803X_DEBUG_PLL_ON BIT(2)
2965 +#define AT803X_DEBUG_RGMII_1V8 BIT(3)
2966 +
2967 +#define MDIO_AZ_DEBUG 0x800D
2968 +
2969 +/* AT803x supports either the XTAL input pad, an internal PLL or the
2970 + * DSP as clock reference for the clock output pad. The XTAL reference
2971 + * is only used for 25 MHz output, all other frequencies need the PLL.
2972 + * The DSP as a clock reference is used in synchronous ethernet
2973 + * applications.
2974 + *
2975 + * By default the PLL is only enabled if there is a link. Otherwise
2976 + * the PHY will go into low power state and disabled the PLL. You can
2977 + * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
2978 + * enabled.
2979 + */
2980 +#define AT803X_MMD7_CLK25M 0x8016
2981 +#define AT803X_CLK_OUT_MASK GENMASK(4, 2)
2982 +#define AT803X_CLK_OUT_25MHZ_XTAL 0
2983 +#define AT803X_CLK_OUT_25MHZ_DSP 1
2984 +#define AT803X_CLK_OUT_50MHZ_PLL 2
2985 +#define AT803X_CLK_OUT_50MHZ_DSP 3
2986 +#define AT803X_CLK_OUT_62_5MHZ_PLL 4
2987 +#define AT803X_CLK_OUT_62_5MHZ_DSP 5
2988 +#define AT803X_CLK_OUT_125MHZ_PLL 6
2989 +#define AT803X_CLK_OUT_125MHZ_DSP 7
2990 +
2991 +/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
2992 + * but doesn't support choosing between XTAL/PLL and DSP.
2993 + */
2994 +#define AT8035_CLK_OUT_MASK GENMASK(4, 3)
2995 +
2996 +#define AT803X_CLK_OUT_STRENGTH_MASK GENMASK(8, 7)
2997 +#define AT803X_CLK_OUT_STRENGTH_FULL 0
2998 +#define AT803X_CLK_OUT_STRENGTH_HALF 1
2999 +#define AT803X_CLK_OUT_STRENGTH_QUARTER 2
3000 +
3001 +#define AT803X_DEFAULT_DOWNSHIFT 5
3002 +#define AT803X_MIN_DOWNSHIFT 2
3003 +#define AT803X_MAX_DOWNSHIFT 9
3004 +
3005 +#define AT803X_MMD3_SMARTEEE_CTL1 0x805b
3006 +#define AT803X_MMD3_SMARTEEE_CTL2 0x805c
3007 +#define AT803X_MMD3_SMARTEEE_CTL3 0x805d
3008 +#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN BIT(8)
3009 +
3010 +#define ATH9331_PHY_ID 0x004dd041
3011 +#define ATH8030_PHY_ID 0x004dd076
3012 +#define ATH8031_PHY_ID 0x004dd074
3013 +#define ATH8032_PHY_ID 0x004dd023
3014 +#define ATH8035_PHY_ID 0x004dd072
3015 +#define AT8030_PHY_ID_MASK 0xffffffef
3016 +
3017 +#define QCA8081_PHY_ID 0x004dd101
3018 +
3019 +#define QCA8327_A_PHY_ID 0x004dd033
3020 +#define QCA8327_B_PHY_ID 0x004dd034
3021 +#define QCA8337_PHY_ID 0x004dd036
3022 +#define QCA9561_PHY_ID 0x004dd042
3023 +#define QCA8K_PHY_ID_MASK 0xffffffff
3024 +
3025 +#define QCA8K_DEVFLAGS_REVISION_MASK GENMASK(2, 0)
3026 +
3027 +#define AT803X_PAGE_FIBER 0
3028 +#define AT803X_PAGE_COPPER 1
3029 +
3030 +/* don't turn off internal PLL */
3031 +#define AT803X_KEEP_PLL_ENABLED BIT(0)
3032 +#define AT803X_DISABLE_SMARTEEE BIT(1)
3033 +
3034 +/* disable hibernation mode */
3035 +#define AT803X_DISABLE_HIBERNATION_MODE BIT(2)
3036 +
3037 +/* ADC threshold */
3038 +#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80
3039 +#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0)
3040 +#define QCA808X_ADC_THRESHOLD_80MV 0
3041 +#define QCA808X_ADC_THRESHOLD_100MV 0xf0
3042 +#define QCA808X_ADC_THRESHOLD_200MV 0x0f
3043 +#define QCA808X_ADC_THRESHOLD_300MV 0xff
3044 +
3045 +/* CLD control */
3046 +#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007
3047 +#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4)
3048 +#define QCA808X_8023AZ_AFE_EN 0x90
3049 +
3050 +/* AZ control */
3051 +#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008
3052 +#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32
3053 +
3054 +#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014
3055 +#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529
3056 +
3057 +#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E
3058 +#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341
3059 +
3060 +#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E
3061 +#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419
3062 +
3063 +#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020
3064 +#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341
3065 +
3066 +#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c
3067 +#define QCA808X_TOP_OPTION1_DATA 0x0
3068 +
3069 +#define QCA808X_PHY_MMD3_DEBUG_1 0xa100
3070 +#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203
3071 +#define QCA808X_PHY_MMD3_DEBUG_2 0xa101
3072 +#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad
3073 +#define QCA808X_PHY_MMD3_DEBUG_3 0xa103
3074 +#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698
3075 +#define QCA808X_PHY_MMD3_DEBUG_4 0xa105
3076 +#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001
3077 +#define QCA808X_PHY_MMD3_DEBUG_5 0xa106
3078 +#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111
3079 +#define QCA808X_PHY_MMD3_DEBUG_6 0xa011
3080 +#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85
3081 +
3082 +/* master/slave seed config */
3083 +#define QCA808X_PHY_DEBUG_LOCAL_SEED 9
3084 +#define QCA808X_MASTER_SLAVE_SEED_ENABLE BIT(1)
3085 +#define QCA808X_MASTER_SLAVE_SEED_CFG GENMASK(12, 2)
3086 +#define QCA808X_MASTER_SLAVE_SEED_RANGE 0x32
3087 +
3088 +/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
3089 + * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
3090 + */
3091 +#define QCA808X_DBG_AN_TEST 0xb
3092 +#define QCA808X_HIBERNATION_EN BIT(15)
3093 +
3094 +#define QCA808X_CDT_ENABLE_TEST BIT(15)
3095 +#define QCA808X_CDT_INTER_CHECK_DIS BIT(13)
3096 +#define QCA808X_CDT_STATUS BIT(11)
3097 +#define QCA808X_CDT_LENGTH_UNIT BIT(10)
3098 +
3099 +#define QCA808X_MMD3_CDT_STATUS 0x8064
3100 +#define QCA808X_MMD3_CDT_DIAG_PAIR_A 0x8065
3101 +#define QCA808X_MMD3_CDT_DIAG_PAIR_B 0x8066
3102 +#define QCA808X_MMD3_CDT_DIAG_PAIR_C 0x8067
3103 +#define QCA808X_MMD3_CDT_DIAG_PAIR_D 0x8068
3104 +#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT GENMASK(15, 8)
3105 +#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT GENMASK(7, 0)
3106 +
3107 +#define QCA808X_CDT_CODE_PAIR_A GENMASK(15, 12)
3108 +#define QCA808X_CDT_CODE_PAIR_B GENMASK(11, 8)
3109 +#define QCA808X_CDT_CODE_PAIR_C GENMASK(7, 4)
3110 +#define QCA808X_CDT_CODE_PAIR_D GENMASK(3, 0)
3111 +
3112 +#define QCA808X_CDT_STATUS_STAT_TYPE GENMASK(1, 0)
3113 +#define QCA808X_CDT_STATUS_STAT_FAIL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
3114 +#define QCA808X_CDT_STATUS_STAT_NORMAL FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
3115 +#define QCA808X_CDT_STATUS_STAT_SAME_OPEN FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
3116 +#define QCA808X_CDT_STATUS_STAT_SAME_SHORT FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
3117 +
3118 +#define QCA808X_CDT_STATUS_STAT_MDI GENMASK(3, 2)
3119 +#define QCA808X_CDT_STATUS_STAT_MDI1 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
3120 +#define QCA808X_CDT_STATUS_STAT_MDI2 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
3121 +#define QCA808X_CDT_STATUS_STAT_MDI3 FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
3122 +
3123 +/* NORMAL are MDI with type set to 0 */
3124 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI1
3125 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
3126 + QCA808X_CDT_STATUS_STAT_MDI1)
3127 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
3128 + QCA808X_CDT_STATUS_STAT_MDI1)
3129 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI2
3130 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
3131 + QCA808X_CDT_STATUS_STAT_MDI2)
3132 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
3133 + QCA808X_CDT_STATUS_STAT_MDI2)
3134 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL QCA808X_CDT_STATUS_STAT_MDI3
3135 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN (QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
3136 + QCA808X_CDT_STATUS_STAT_MDI3)
3137 +#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT (QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
3138 + QCA808X_CDT_STATUS_STAT_MDI3)
3139 +
3140 +/* Added for reference of existence but should be handled by wait_for_completion already */
3141 +#define QCA808X_CDT_STATUS_STAT_BUSY (BIT(1) | BIT(3))
3142 +
3143 +#define QCA808X_MMD7_LED_GLOBAL 0x8073
3144 +#define QCA808X_LED_BLINK_1 GENMASK(11, 6)
3145 +#define QCA808X_LED_BLINK_2 GENMASK(5, 0)
3146 +/* Values are the same for both BLINK_1 and BLINK_2 */
3147 +#define QCA808X_LED_BLINK_FREQ_MASK GENMASK(5, 3)
3148 +#define QCA808X_LED_BLINK_FREQ_2HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
3149 +#define QCA808X_LED_BLINK_FREQ_4HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
3150 +#define QCA808X_LED_BLINK_FREQ_8HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
3151 +#define QCA808X_LED_BLINK_FREQ_16HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
3152 +#define QCA808X_LED_BLINK_FREQ_32HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
3153 +#define QCA808X_LED_BLINK_FREQ_64HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
3154 +#define QCA808X_LED_BLINK_FREQ_128HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
3155 +#define QCA808X_LED_BLINK_FREQ_256HZ FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
3156 +#define QCA808X_LED_BLINK_DUTY_MASK GENMASK(2, 0)
3157 +#define QCA808X_LED_BLINK_DUTY_50_50 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
3158 +#define QCA808X_LED_BLINK_DUTY_75_25 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
3159 +#define QCA808X_LED_BLINK_DUTY_25_75 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
3160 +#define QCA808X_LED_BLINK_DUTY_33_67 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
3161 +#define QCA808X_LED_BLINK_DUTY_67_33 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
3162 +#define QCA808X_LED_BLINK_DUTY_17_83 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
3163 +#define QCA808X_LED_BLINK_DUTY_83_17 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
3164 +#define QCA808X_LED_BLINK_DUTY_8_92 FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
3165 +
3166 +#define QCA808X_MMD7_LED2_CTRL 0x8074
3167 +#define QCA808X_MMD7_LED2_FORCE_CTRL 0x8075
3168 +#define QCA808X_MMD7_LED1_CTRL 0x8076
3169 +#define QCA808X_MMD7_LED1_FORCE_CTRL 0x8077
3170 +#define QCA808X_MMD7_LED0_CTRL 0x8078
3171 +#define QCA808X_MMD7_LED_CTRL(x) (0x8078 - ((x) * 2))
3172 +
3173 +/* LED hw control pattern is the same for every LED */
3174 +#define QCA808X_LED_PATTERN_MASK GENMASK(15, 0)
3175 +#define QCA808X_LED_SPEED2500_ON BIT(15)
3176 +#define QCA808X_LED_SPEED2500_BLINK BIT(14)
3177 +/* Follow blink trigger even if duplex or speed condition doesn't match */
3178 +#define QCA808X_LED_BLINK_CHECK_BYPASS BIT(13)
3179 +#define QCA808X_LED_FULL_DUPLEX_ON BIT(12)
3180 +#define QCA808X_LED_HALF_DUPLEX_ON BIT(11)
3181 +#define QCA808X_LED_TX_BLINK BIT(10)
3182 +#define QCA808X_LED_RX_BLINK BIT(9)
3183 +#define QCA808X_LED_TX_ON_10MS BIT(8)
3184 +#define QCA808X_LED_RX_ON_10MS BIT(7)
3185 +#define QCA808X_LED_SPEED1000_ON BIT(6)
3186 +#define QCA808X_LED_SPEED100_ON BIT(5)
3187 +#define QCA808X_LED_SPEED10_ON BIT(4)
3188 +#define QCA808X_LED_COLLISION_BLINK BIT(3)
3189 +#define QCA808X_LED_SPEED1000_BLINK BIT(2)
3190 +#define QCA808X_LED_SPEED100_BLINK BIT(1)
3191 +#define QCA808X_LED_SPEED10_BLINK BIT(0)
3192 +
3193 +#define QCA808X_MMD7_LED0_FORCE_CTRL 0x8079
3194 +#define QCA808X_MMD7_LED_FORCE_CTRL(x) (0x8079 - ((x) * 2))
3195 +
3196 +/* LED force ctrl is the same for every LED
3197 + * No documentation exist for this, not even internal one
3198 + * with NDA as QCOM gives only info about configuring
3199 + * hw control pattern rules and doesn't indicate any way
3200 + * to force the LED to specific mode.
3201 + * These define comes from reverse and testing and maybe
3202 + * lack of some info or some info are not entirely correct.
3203 + * For the basic LED control and hw control these finding
3204 + * are enough to support LED control in all the required APIs.
3205 + *
3206 + * On doing some comparison with implementation with qca807x,
3207 + * it was found that it's 1:1 equal to it and confirms all the
3208 + * reverse done. It was also found further specification with the
3209 + * force mode and the blink modes.
3210 + */
3211 +#define QCA808X_LED_FORCE_EN BIT(15)
3212 +#define QCA808X_LED_FORCE_MODE_MASK GENMASK(14, 13)
3213 +#define QCA808X_LED_FORCE_BLINK_1 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
3214 +#define QCA808X_LED_FORCE_BLINK_2 FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
3215 +#define QCA808X_LED_FORCE_ON FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
3216 +#define QCA808X_LED_FORCE_OFF FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
3217 +
3218 +#define QCA808X_MMD7_LED_POLARITY_CTRL 0x901a
3219 +/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
3220 + * LED to active high. It's not clear what BIT 3 and BIT 4 does.
3221 + */
3222 +#define QCA808X_LED_ACTIVE_HIGH BIT(6)
3223 +
3224 +/* QCA808X 1G chip type */
3225 +#define QCA808X_PHY_MMD7_CHIP_TYPE 0x901d
3226 +#define QCA808X_PHY_CHIP_TYPE_1G BIT(0)
3227 +
3228 +#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072
3229 +#define QCA8081_PHY_FIFO_RSTN BIT(11)
3230 +
3231 +MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
3232 +MODULE_AUTHOR("Matus Ujhelyi");
3233 +MODULE_LICENSE("GPL");
3234 +
3235 +enum stat_access_type {
3236 + PHY,
3237 + MMD
3238 +};
3239 +
3240 +struct at803x_hw_stat {
3241 + const char *string;
3242 + u8 reg;
3243 + u32 mask;
3244 + enum stat_access_type access_type;
3245 +};
3246 +
3247 +static struct at803x_hw_stat qca83xx_hw_stats[] = {
3248 + { "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
3249 + { "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
3250 + { "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
3251 +};
3252 +
3253 +struct at803x_ss_mask {
3254 + u16 speed_mask;
3255 + u8 speed_shift;
3256 +};
3257 +
3258 +struct at803x_priv {
3259 + int flags;
3260 + u16 clk_25m_reg;
3261 + u16 clk_25m_mask;
3262 + u8 smarteee_lpi_tw_1g;
3263 + u8 smarteee_lpi_tw_100m;
3264 + bool is_fiber;
3265 + bool is_1000basex;
3266 + struct regulator_dev *vddio_rdev;
3267 + struct regulator_dev *vddh_rdev;
3268 + u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
3269 + int led_polarity_mode;
3270 +};
3271 +
3272 +struct at803x_context {
3273 + u16 bmcr;
3274 + u16 advertise;
3275 + u16 control1000;
3276 + u16 int_enable;
3277 + u16 smart_speed;
3278 + u16 led_control;
3279 +};
3280 +
3281 +static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
3282 +{
3283 + int ret;
3284 +
3285 + ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
3286 + if (ret < 0)
3287 + return ret;
3288 +
3289 + return phy_write(phydev, AT803X_DEBUG_DATA, data);
3290 +}
3291 +
3292 +static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
3293 +{
3294 + int ret;
3295 +
3296 + ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
3297 + if (ret < 0)
3298 + return ret;
3299 +
3300 + return phy_read(phydev, AT803X_DEBUG_DATA);
3301 +}
3302 +
3303 +static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
3304 + u16 clear, u16 set)
3305 +{
3306 + u16 val;
3307 + int ret;
3308 +
3309 + ret = at803x_debug_reg_read(phydev, reg);
3310 + if (ret < 0)
3311 + return ret;
3312 +
3313 + val = ret & 0xffff;
3314 + val &= ~clear;
3315 + val |= set;
3316 +
3317 + return phy_write(phydev, AT803X_DEBUG_DATA, val);
3318 +}
3319 +
3320 +static int at803x_write_page(struct phy_device *phydev, int page)
3321 +{
3322 + int mask;
3323 + int set;
3324 +
3325 + if (page == AT803X_PAGE_COPPER) {
3326 + set = AT803X_BT_BX_REG_SEL;
3327 + mask = 0;
3328 + } else {
3329 + set = 0;
3330 + mask = AT803X_BT_BX_REG_SEL;
3331 + }
3332 +
3333 + return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
3334 +}
3335 +
3336 +static int at803x_read_page(struct phy_device *phydev)
3337 +{
3338 + int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
3339 +
3340 + if (ccr < 0)
3341 + return ccr;
3342 +
3343 + if (ccr & AT803X_BT_BX_REG_SEL)
3344 + return AT803X_PAGE_COPPER;
3345 +
3346 + return AT803X_PAGE_FIBER;
3347 +}
3348 +
3349 +static int at803x_enable_rx_delay(struct phy_device *phydev)
3350 +{
3351 + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
3352 + AT803X_DEBUG_RX_CLK_DLY_EN);
3353 +}
3354 +
3355 +static int at803x_enable_tx_delay(struct phy_device *phydev)
3356 +{
3357 + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
3358 + AT803X_DEBUG_TX_CLK_DLY_EN);
3359 +}
3360 +
3361 +static int at803x_disable_rx_delay(struct phy_device *phydev)
3362 +{
3363 + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
3364 + AT803X_DEBUG_RX_CLK_DLY_EN, 0);
3365 +}
3366 +
3367 +static int at803x_disable_tx_delay(struct phy_device *phydev)
3368 +{
3369 + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
3370 + AT803X_DEBUG_TX_CLK_DLY_EN, 0);
3371 +}
3372 +
3373 +/* save relevant PHY registers to private copy */
3374 +static void at803x_context_save(struct phy_device *phydev,
3375 + struct at803x_context *context)
3376 +{
3377 + context->bmcr = phy_read(phydev, MII_BMCR);
3378 + context->advertise = phy_read(phydev, MII_ADVERTISE);
3379 + context->control1000 = phy_read(phydev, MII_CTRL1000);
3380 + context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
3381 + context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
3382 + context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
3383 +}
3384 +
3385 +/* restore relevant PHY registers from private copy */
3386 +static void at803x_context_restore(struct phy_device *phydev,
3387 + const struct at803x_context *context)
3388 +{
3389 + phy_write(phydev, MII_BMCR, context->bmcr);
3390 + phy_write(phydev, MII_ADVERTISE, context->advertise);
3391 + phy_write(phydev, MII_CTRL1000, context->control1000);
3392 + phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
3393 + phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
3394 + phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
3395 +}
3396 +
3397 +static int at803x_set_wol(struct phy_device *phydev,
3398 + struct ethtool_wolinfo *wol)
3399 +{
3400 + int ret, irq_enabled;
3401 +
3402 + if (wol->wolopts & WAKE_MAGIC) {
3403 + struct net_device *ndev = phydev->attached_dev;
3404 + const u8 *mac;
3405 + unsigned int i;
3406 + static const unsigned int offsets[] = {
3407 + AT803X_LOC_MAC_ADDR_32_47_OFFSET,
3408 + AT803X_LOC_MAC_ADDR_16_31_OFFSET,
3409 + AT803X_LOC_MAC_ADDR_0_15_OFFSET,
3410 + };
3411 +
3412 + if (!ndev)
3413 + return -ENODEV;
3414 +
3415 + mac = (const u8 *)ndev->dev_addr;
3416 +
3417 + if (!is_valid_ether_addr(mac))
3418 + return -EINVAL;
3419 +
3420 + for (i = 0; i < 3; i++)
3421 + phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
3422 + mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
3423 +
3424 + /* Enable WOL interrupt */
3425 + ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
3426 + if (ret)
3427 + return ret;
3428 + } else {
3429 + /* Disable WOL interrupt */
3430 + ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
3431 + if (ret)
3432 + return ret;
3433 + }
3434 +
3435 + /* Clear WOL status */
3436 + ret = phy_read(phydev, AT803X_INTR_STATUS);
3437 + if (ret < 0)
3438 + return ret;
3439 +
3440 + /* Check if there are other interrupts except for WOL triggered when PHY is
3441 + * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
3442 + * be passed up to the interrupt PIN.
3443 + */
3444 + irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
3445 + if (irq_enabled < 0)
3446 + return irq_enabled;
3447 +
3448 + irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
3449 + if (ret & irq_enabled && !phy_polling_mode(phydev))
3450 + phy_trigger_machine(phydev);
3451 +
3452 + return 0;
3453 +}
3454 +
3455 +static void at803x_get_wol(struct phy_device *phydev,
3456 + struct ethtool_wolinfo *wol)
3457 +{
3458 + int value;
3459 +
3460 + wol->supported = WAKE_MAGIC;
3461 + wol->wolopts = 0;
3462 +
3463 + value = phy_read(phydev, AT803X_INTR_ENABLE);
3464 + if (value < 0)
3465 + return;
3466 +
3467 + if (value & AT803X_INTR_ENABLE_WOL)
3468 + wol->wolopts |= WAKE_MAGIC;
3469 +}
3470 +
3471 +static int qca83xx_get_sset_count(struct phy_device *phydev)
3472 +{
3473 + return ARRAY_SIZE(qca83xx_hw_stats);
3474 +}
3475 +
3476 +static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
3477 +{
3478 + int i;
3479 +
3480 + for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
3481 + strscpy(data + i * ETH_GSTRING_LEN,
3482 + qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
3483 + }
3484 +}
3485 +
3486 +static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
3487 +{
3488 + struct at803x_hw_stat stat = qca83xx_hw_stats[i];
3489 + struct at803x_priv *priv = phydev->priv;
3490 + int val;
3491 + u64 ret;
3492 +
3493 + if (stat.access_type == MMD)
3494 + val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
3495 + else
3496 + val = phy_read(phydev, stat.reg);
3497 +
3498 + if (val < 0) {
3499 + ret = U64_MAX;
3500 + } else {
3501 + val = val & stat.mask;
3502 + priv->stats[i] += val;
3503 + ret = priv->stats[i];
3504 + }
3505 +
3506 + return ret;
3507 +}
3508 +
3509 +static void qca83xx_get_stats(struct phy_device *phydev,
3510 + struct ethtool_stats *stats, u64 *data)
3511 +{
3512 + int i;
3513 +
3514 + for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
3515 + data[i] = qca83xx_get_stat(phydev, i);
3516 +}
3517 +
3518 +static int at803x_suspend(struct phy_device *phydev)
3519 +{
3520 + int value;
3521 + int wol_enabled;
3522 +
3523 + value = phy_read(phydev, AT803X_INTR_ENABLE);
3524 + wol_enabled = value & AT803X_INTR_ENABLE_WOL;
3525 +
3526 + if (wol_enabled)
3527 + value = BMCR_ISOLATE;
3528 + else
3529 + value = BMCR_PDOWN;
3530 +
3531 + phy_modify(phydev, MII_BMCR, 0, value);
3532 +
3533 + return 0;
3534 +}
3535 +
3536 +static int at803x_resume(struct phy_device *phydev)
3537 +{
3538 + return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
3539 +}
3540 +
3541 +static int at803x_parse_dt(struct phy_device *phydev)
3542 +{
3543 + struct device_node *node = phydev->mdio.dev.of_node;
3544 + struct at803x_priv *priv = phydev->priv;
3545 + u32 freq, strength, tw;
3546 + unsigned int sel;
3547 + int ret;
3548 +
3549 + if (!IS_ENABLED(CONFIG_OF_MDIO))
3550 + return 0;
3551 +
3552 + if (of_property_read_bool(node, "qca,disable-smarteee"))
3553 + priv->flags |= AT803X_DISABLE_SMARTEEE;
3554 +
3555 + if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
3556 + priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
3557 +
3558 + if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
3559 + if (!tw || tw > 255) {
3560 + phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
3561 + return -EINVAL;
3562 + }
3563 + priv->smarteee_lpi_tw_1g = tw;
3564 + }
3565 +
3566 + if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
3567 + if (!tw || tw > 255) {
3568 + phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
3569 + return -EINVAL;
3570 + }
3571 + priv->smarteee_lpi_tw_100m = tw;
3572 + }
3573 +
3574 + ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
3575 + if (!ret) {
3576 + switch (freq) {
3577 + case 25000000:
3578 + sel = AT803X_CLK_OUT_25MHZ_XTAL;
3579 + break;
3580 + case 50000000:
3581 + sel = AT803X_CLK_OUT_50MHZ_PLL;
3582 + break;
3583 + case 62500000:
3584 + sel = AT803X_CLK_OUT_62_5MHZ_PLL;
3585 + break;
3586 + case 125000000:
3587 + sel = AT803X_CLK_OUT_125MHZ_PLL;
3588 + break;
3589 + default:
3590 + phydev_err(phydev, "invalid qca,clk-out-frequency\n");
3591 + return -EINVAL;
3592 + }
3593 +
3594 + priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
3595 + priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
3596 + }
3597 +
3598 + ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
3599 + if (!ret) {
3600 + priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
3601 + switch (strength) {
3602 + case AR803X_STRENGTH_FULL:
3603 + priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
3604 + break;
3605 + case AR803X_STRENGTH_HALF:
3606 + priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
3607 + break;
3608 + case AR803X_STRENGTH_QUARTER:
3609 + priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
3610 + break;
3611 + default:
3612 + phydev_err(phydev, "invalid qca,clk-out-strength\n");
3613 + return -EINVAL;
3614 + }
3615 + }
3616 +
3617 + return 0;
3618 +}
3619 +
3620 +static int at803x_probe(struct phy_device *phydev)
3621 +{
3622 + struct device *dev = &phydev->mdio.dev;
3623 + struct at803x_priv *priv;
3624 + int ret;
3625 +
3626 + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
3627 + if (!priv)
3628 + return -ENOMEM;
3629 +
3630 + /* Init LED polarity mode to -1 */
3631 + priv->led_polarity_mode = -1;
3632 +
3633 + phydev->priv = priv;
3634 +
3635 + ret = at803x_parse_dt(phydev);
3636 + if (ret)
3637 + return ret;
3638 +
3639 + return 0;
3640 +}
3641 +
3642 +static int at803x_get_features(struct phy_device *phydev)
3643 +{
3644 + struct at803x_priv *priv = phydev->priv;
3645 + int err;
3646 +
3647 + err = genphy_read_abilities(phydev);
3648 + if (err)
3649 + return err;
3650 +
3651 + if (phydev->drv->phy_id != ATH8031_PHY_ID)
3652 + return 0;
3653 +
3654 + /* AR8031/AR8033 have different status registers
3655 + * for copper and fiber operation. However, the
3656 + * extended status register is the same for both
3657 + * operation modes.
3658 + *
3659 + * As a result of that, ESTATUS_1000_XFULL is set
3660 + * to 1 even when operating in copper TP mode.
3661 + *
3662 + * Remove this mode from the supported link modes
3663 + * when not operating in 1000BaseX mode.
3664 + */
3665 + if (!priv->is_1000basex)
3666 + linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
3667 + phydev->supported);
3668 +
3669 + return 0;
3670 +}
3671 +
3672 +static int at803x_smarteee_config(struct phy_device *phydev)
3673 +{
3674 + struct at803x_priv *priv = phydev->priv;
3675 + u16 mask = 0, val = 0;
3676 + int ret;
3677 +
3678 + if (priv->flags & AT803X_DISABLE_SMARTEEE)
3679 + return phy_modify_mmd(phydev, MDIO_MMD_PCS,
3680 + AT803X_MMD3_SMARTEEE_CTL3,
3681 + AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
3682 +
3683 + if (priv->smarteee_lpi_tw_1g) {
3684 + mask |= 0xff00;
3685 + val |= priv->smarteee_lpi_tw_1g << 8;
3686 + }
3687 + if (priv->smarteee_lpi_tw_100m) {
3688 + mask |= 0x00ff;
3689 + val |= priv->smarteee_lpi_tw_100m;
3690 + }
3691 + if (!mask)
3692 + return 0;
3693 +
3694 + ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
3695 + mask, val);
3696 + if (ret)
3697 + return ret;
3698 +
3699 + return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
3700 + AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
3701 + AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
3702 +}
3703 +
3704 +static int at803x_clk_out_config(struct phy_device *phydev)
3705 +{
3706 + struct at803x_priv *priv = phydev->priv;
3707 +
3708 + if (!priv->clk_25m_mask)
3709 + return 0;
3710 +
3711 + return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
3712 + priv->clk_25m_mask, priv->clk_25m_reg);
3713 +}
3714 +
3715 +static int at8031_pll_config(struct phy_device *phydev)
3716 +{
3717 + struct at803x_priv *priv = phydev->priv;
3718 +
3719 + /* The default after hardware reset is PLL OFF. After a soft reset, the
3720 + * values are retained.
3721 + */
3722 + if (priv->flags & AT803X_KEEP_PLL_ENABLED)
3723 + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
3724 + 0, AT803X_DEBUG_PLL_ON);
3725 + else
3726 + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
3727 + AT803X_DEBUG_PLL_ON, 0);
3728 +}
3729 +
3730 +static int at803x_hibernation_mode_config(struct phy_device *phydev)
3731 +{
3732 + struct at803x_priv *priv = phydev->priv;
3733 +
3734 + /* The default after hardware reset is hibernation mode enabled. After
3735 + * software reset, the value is retained.
3736 + */
3737 + if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
3738 + return 0;
3739 +
3740 + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
3741 + AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
3742 +}
3743 +
3744 +static int at803x_config_init(struct phy_device *phydev)
3745 +{
3746 + int ret;
3747 +
3748 + /* The RX and TX delay default is:
3749 + * after HW reset: RX delay enabled and TX delay disabled
3750 + * after SW reset: RX delay enabled, while TX delay retains the
3751 + * value before reset.
3752 + */
3753 + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
3754 + phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
3755 + ret = at803x_enable_rx_delay(phydev);
3756 + else
3757 + ret = at803x_disable_rx_delay(phydev);
3758 + if (ret < 0)
3759 + return ret;
3760 +
3761 + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
3762 + phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
3763 + ret = at803x_enable_tx_delay(phydev);
3764 + else
3765 + ret = at803x_disable_tx_delay(phydev);
3766 + if (ret < 0)
3767 + return ret;
3768 +
3769 + ret = at803x_smarteee_config(phydev);
3770 + if (ret < 0)
3771 + return ret;
3772 +
3773 + ret = at803x_clk_out_config(phydev);
3774 + if (ret < 0)
3775 + return ret;
3776 +
3777 + ret = at803x_hibernation_mode_config(phydev);
3778 + if (ret < 0)
3779 + return ret;
3780 +
3781 + /* Ar803x extended next page bit is enabled by default. Cisco
3782 + * multigig switches read this bit and attempt to negotiate 10Gbps
3783 + * rates even if the next page bit is disabled. This is incorrect
3784 + * behaviour but we still need to accommodate it. XNP is only needed
3785 + * for 10Gbps support, so disable XNP.
3786 + */
3787 + return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
3788 +}
3789 +
3790 +static int at803x_ack_interrupt(struct phy_device *phydev)
3791 +{
3792 + int err;
3793 +
3794 + err = phy_read(phydev, AT803X_INTR_STATUS);
3795 +
3796 + return (err < 0) ? err : 0;
3797 +}
3798 +
3799 +static int at803x_config_intr(struct phy_device *phydev)
3800 +{
3801 + int err;
3802 + int value;
3803 +
3804 + value = phy_read(phydev, AT803X_INTR_ENABLE);
3805 +
3806 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
3807 + /* Clear any pending interrupts */
3808 + err = at803x_ack_interrupt(phydev);
3809 + if (err)
3810 + return err;
3811 +
3812 + value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
3813 + value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
3814 + value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
3815 + value |= AT803X_INTR_ENABLE_LINK_FAIL;
3816 + value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
3817 +
3818 + err = phy_write(phydev, AT803X_INTR_ENABLE, value);
3819 + } else {
3820 + err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
3821 + if (err)
3822 + return err;
3823 +
3824 + /* Clear any pending interrupts */
3825 + err = at803x_ack_interrupt(phydev);
3826 + }
3827 +
3828 + return err;
3829 +}
3830 +
3831 +static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
3832 +{
3833 + int irq_status, int_enabled;
3834 +
3835 + irq_status = phy_read(phydev, AT803X_INTR_STATUS);
3836 + if (irq_status < 0) {
3837 + phy_error(phydev);
3838 + return IRQ_NONE;
3839 + }
3840 +
3841 + /* Read the current enabled interrupts */
3842 + int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
3843 + if (int_enabled < 0) {
3844 + phy_error(phydev);
3845 + return IRQ_NONE;
3846 + }
3847 +
3848 + /* See if this was one of our enabled interrupts */
3849 + if (!(irq_status & int_enabled))
3850 + return IRQ_NONE;
3851 +
3852 + phy_trigger_machine(phydev);
3853 +
3854 + return IRQ_HANDLED;
3855 +}
3856 +
3857 +static void at803x_link_change_notify(struct phy_device *phydev)
3858 +{
3859 + /*
3860 + * Conduct a hardware reset for AT8030 every time a link loss is
3861 + * signalled. This is necessary to circumvent a hardware bug that
3862 + * occurs when the cable is unplugged while TX packets are pending
3863 + * in the FIFO. In such cases, the FIFO enters an error mode it
3864 + * cannot recover from by software.
3865 + */
3866 + if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
3867 + struct at803x_context context;
3868 +
3869 + at803x_context_save(phydev, &context);
3870 +
3871 + phy_device_reset(phydev, 1);
3872 + usleep_range(1000, 2000);
3873 + phy_device_reset(phydev, 0);
3874 + usleep_range(1000, 2000);
3875 +
3876 + at803x_context_restore(phydev, &context);
3877 +
3878 + phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
3879 + }
3880 +}
3881 +
3882 +static int at803x_read_specific_status(struct phy_device *phydev,
3883 + struct at803x_ss_mask ss_mask)
3884 +{
3885 + int ss;
3886 +
3887 + /* Read the AT8035 PHY-Specific Status register, which indicates the
3888 + * speed and duplex that the PHY is actually using, irrespective of
3889 + * whether we are in autoneg mode or not.
3890 + */
3891 + ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
3892 + if (ss < 0)
3893 + return ss;
3894 +
3895 + if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
3896 + int sfc, speed;
3897 +
3898 + sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
3899 + if (sfc < 0)
3900 + return sfc;
3901 +
3902 + speed = ss & ss_mask.speed_mask;
3903 + speed >>= ss_mask.speed_shift;
3904 +
3905 + switch (speed) {
3906 + case AT803X_SS_SPEED_10:
3907 + phydev->speed = SPEED_10;
3908 + break;
3909 + case AT803X_SS_SPEED_100:
3910 + phydev->speed = SPEED_100;
3911 + break;
3912 + case AT803X_SS_SPEED_1000:
3913 + phydev->speed = SPEED_1000;
3914 + break;
3915 + case QCA808X_SS_SPEED_2500:
3916 + phydev->speed = SPEED_2500;
3917 + break;
3918 + }
3919 + if (ss & AT803X_SS_DUPLEX)
3920 + phydev->duplex = DUPLEX_FULL;
3921 + else
3922 + phydev->duplex = DUPLEX_HALF;
3923 +
3924 + if (ss & AT803X_SS_MDIX)
3925 + phydev->mdix = ETH_TP_MDI_X;
3926 + else
3927 + phydev->mdix = ETH_TP_MDI;
3928 +
3929 + switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
3930 + case AT803X_SFC_MANUAL_MDI:
3931 + phydev->mdix_ctrl = ETH_TP_MDI;
3932 + break;
3933 + case AT803X_SFC_MANUAL_MDIX:
3934 + phydev->mdix_ctrl = ETH_TP_MDI_X;
3935 + break;
3936 + case AT803X_SFC_AUTOMATIC_CROSSOVER:
3937 + phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
3938 + break;
3939 + }
3940 + }
3941 +
3942 + return 0;
3943 +}
3944 +
3945 +static int at803x_read_status(struct phy_device *phydev)
3946 +{
3947 + struct at803x_ss_mask ss_mask = { 0 };
3948 + int err, old_link = phydev->link;
3949 +
3950 + /* Update the link, but return if there was an error */
3951 + err = genphy_update_link(phydev);
3952 + if (err)
3953 + return err;
3954 +
3955 + /* why bother the PHY if nothing can have changed */
3956 + if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
3957 + return 0;
3958 +
3959 + phydev->speed = SPEED_UNKNOWN;
3960 + phydev->duplex = DUPLEX_UNKNOWN;
3961 + phydev->pause = 0;
3962 + phydev->asym_pause = 0;
3963 +
3964 + err = genphy_read_lpa(phydev);
3965 + if (err < 0)
3966 + return err;
3967 +
3968 + ss_mask.speed_mask = AT803X_SS_SPEED_MASK;
3969 + ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
3970 + err = at803x_read_specific_status(phydev, ss_mask);
3971 + if (err < 0)
3972 + return err;
3973 +
3974 + if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
3975 + phy_resolve_aneg_pause(phydev);
3976 +
3977 + return 0;
3978 +}
3979 +
3980 +static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
3981 +{
3982 + u16 val;
3983 +
3984 + switch (ctrl) {
3985 + case ETH_TP_MDI:
3986 + val = AT803X_SFC_MANUAL_MDI;
3987 + break;
3988 + case ETH_TP_MDI_X:
3989 + val = AT803X_SFC_MANUAL_MDIX;
3990 + break;
3991 + case ETH_TP_MDI_AUTO:
3992 + val = AT803X_SFC_AUTOMATIC_CROSSOVER;
3993 + break;
3994 + default:
3995 + return 0;
3996 + }
3997 +
3998 + return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
3999 + AT803X_SFC_MDI_CROSSOVER_MODE_M,
4000 + FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
4001 +}
4002 +
4003 +static int at803x_prepare_config_aneg(struct phy_device *phydev)
4004 +{
4005 + int ret;
4006 +
4007 + ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
4008 + if (ret < 0)
4009 + return ret;
4010 +
4011 + /* Changes of the midx bits are disruptive to the normal operation;
4012 + * therefore any changes to these registers must be followed by a
4013 + * software reset to take effect.
4014 + */
4015 + if (ret == 1) {
4016 + ret = genphy_soft_reset(phydev);
4017 + if (ret < 0)
4018 + return ret;
4019 + }
4020 +
4021 + return 0;
4022 +}
4023 +
4024 +static int at803x_config_aneg(struct phy_device *phydev)
4025 +{
4026 + struct at803x_priv *priv = phydev->priv;
4027 + int ret;
4028 +
4029 + ret = at803x_prepare_config_aneg(phydev);
4030 + if (ret)
4031 + return ret;
4032 +
4033 + if (priv->is_1000basex)
4034 + return genphy_c37_config_aneg(phydev);
4035 +
4036 + return genphy_config_aneg(phydev);
4037 +}
4038 +
4039 +static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
4040 +{
4041 + int val;
4042 +
4043 + val = phy_read(phydev, AT803X_SMART_SPEED);
4044 + if (val < 0)
4045 + return val;
4046 +
4047 + if (val & AT803X_SMART_SPEED_ENABLE)
4048 + *d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
4049 + else
4050 + *d = DOWNSHIFT_DEV_DISABLE;
4051 +
4052 + return 0;
4053 +}
4054 +
4055 +static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
4056 +{
4057 + u16 mask, set;
4058 + int ret;
4059 +
4060 + switch (cnt) {
4061 + case DOWNSHIFT_DEV_DEFAULT_COUNT:
4062 + cnt = AT803X_DEFAULT_DOWNSHIFT;
4063 + fallthrough;
4064 + case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
4065 + set = AT803X_SMART_SPEED_ENABLE |
4066 + AT803X_SMART_SPEED_BYPASS_TIMER |
4067 + FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
4068 + mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
4069 + break;
4070 + case DOWNSHIFT_DEV_DISABLE:
4071 + set = 0;
4072 + mask = AT803X_SMART_SPEED_ENABLE |
4073 + AT803X_SMART_SPEED_BYPASS_TIMER;
4074 + break;
4075 + default:
4076 + return -EINVAL;
4077 + }
4078 +
4079 + ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
4080 +
4081 + /* After changing the smart speed settings, we need to perform a
4082 + * software reset, use phy_init_hw() to make sure we set the
4083 + * reapply any values which might got lost during software reset.
4084 + */
4085 + if (ret == 1)
4086 + ret = phy_init_hw(phydev);
4087 +
4088 + return ret;
4089 +}
4090 +
4091 +static int at803x_get_tunable(struct phy_device *phydev,
4092 + struct ethtool_tunable *tuna, void *data)
4093 +{
4094 + switch (tuna->id) {
4095 + case ETHTOOL_PHY_DOWNSHIFT:
4096 + return at803x_get_downshift(phydev, data);
4097 + default:
4098 + return -EOPNOTSUPP;
4099 + }
4100 +}
4101 +
4102 +static int at803x_set_tunable(struct phy_device *phydev,
4103 + struct ethtool_tunable *tuna, const void *data)
4104 +{
4105 + switch (tuna->id) {
4106 + case ETHTOOL_PHY_DOWNSHIFT:
4107 + return at803x_set_downshift(phydev, *(const u8 *)data);
4108 + default:
4109 + return -EOPNOTSUPP;
4110 + }
4111 +}
4112 +
4113 +static int at803x_cable_test_result_trans(u16 status)
4114 +{
4115 + switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
4116 + case AT803X_CDT_STATUS_STAT_NORMAL:
4117 + return ETHTOOL_A_CABLE_RESULT_CODE_OK;
4118 + case AT803X_CDT_STATUS_STAT_SHORT:
4119 + return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
4120 + case AT803X_CDT_STATUS_STAT_OPEN:
4121 + return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
4122 + case AT803X_CDT_STATUS_STAT_FAIL:
4123 + default:
4124 + return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
4125 + }
4126 +}
4127 +
4128 +static bool at803x_cdt_test_failed(u16 status)
4129 +{
4130 + return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
4131 + AT803X_CDT_STATUS_STAT_FAIL;
4132 +}
4133 +
4134 +static bool at803x_cdt_fault_length_valid(u16 status)
4135 +{
4136 + switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
4137 + case AT803X_CDT_STATUS_STAT_OPEN:
4138 + case AT803X_CDT_STATUS_STAT_SHORT:
4139 + return true;
4140 + }
4141 + return false;
4142 +}
4143 +
4144 +static int at803x_cdt_fault_length(int dt)
4145 +{
4146 + /* According to the datasheet the distance to the fault is
4147 + * DELTA_TIME * 0.824 meters.
4148 + *
4149 + * The author suspect the correct formula is:
4150 + *
4151 + * fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
4152 + *
4153 + * where c is the speed of light, VF is the velocity factor of
4154 + * the twisted pair cable, 125MHz the counter frequency and
4155 + * we need to divide by 2 because the hardware will measure the
4156 + * round trip time to the fault and back to the PHY.
4157 + *
4158 + * With a VF of 0.69 we get the factor 0.824 mentioned in the
4159 + * datasheet.
4160 + */
4161 + return (dt * 824) / 10;
4162 +}
4163 +
4164 +static int at803x_cdt_start(struct phy_device *phydev,
4165 + u32 cdt_start)
4166 +{
4167 + return phy_write(phydev, AT803X_CDT, cdt_start);
4168 +}
4169 +
4170 +static int at803x_cdt_wait_for_completion(struct phy_device *phydev,
4171 + u32 cdt_en)
4172 +{
4173 + int val, ret;
4174 +
4175 + /* One test run takes about 25ms */
4176 + ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
4177 + !(val & cdt_en),
4178 + 30000, 100000, true);
4179 +
4180 + return ret < 0 ? ret : 0;
4181 +}
4182 +
4183 +static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
4184 +{
4185 + static const int ethtool_pair[] = {
4186 + ETHTOOL_A_CABLE_PAIR_A,
4187 + ETHTOOL_A_CABLE_PAIR_B,
4188 + ETHTOOL_A_CABLE_PAIR_C,
4189 + ETHTOOL_A_CABLE_PAIR_D,
4190 + };
4191 + int ret, val;
4192 +
4193 + val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
4194 + AT803X_CDT_ENABLE_TEST;
4195 + ret = at803x_cdt_start(phydev, val);
4196 + if (ret)
4197 + return ret;
4198 +
4199 + ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
4200 + if (ret)
4201 + return ret;
4202 +
4203 + val = phy_read(phydev, AT803X_CDT_STATUS);
4204 + if (val < 0)
4205 + return val;
4206 +
4207 + if (at803x_cdt_test_failed(val))
4208 + return 0;
4209 +
4210 + ethnl_cable_test_result(phydev, ethtool_pair[pair],
4211 + at803x_cable_test_result_trans(val));
4212 +
4213 + if (at803x_cdt_fault_length_valid(val)) {
4214 + val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
4215 + ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
4216 + at803x_cdt_fault_length(val));
4217 + }
4218 +
4219 + return 1;
4220 +}
4221 +
4222 +static int at803x_cable_test_get_status(struct phy_device *phydev,
4223 + bool *finished, unsigned long pair_mask)
4224 +{
4225 + int retries = 20;
4226 + int pair, ret;
4227 +
4228 + *finished = false;
4229 +
4230 + /* According to the datasheet the CDT can be performed when
4231 + * there is no link partner or when the link partner is
4232 + * auto-negotiating. Starting the test will restart the AN
4233 + * automatically. It seems that doing this repeatedly we will
4234 + * get a slot where our link partner won't disturb our
4235 + * measurement.
4236 + */
4237 + while (pair_mask && retries--) {
4238 + for_each_set_bit(pair, &pair_mask, 4) {
4239 + ret = at803x_cable_test_one_pair(phydev, pair);
4240 + if (ret < 0)
4241 + return ret;
4242 + if (ret)
4243 + clear_bit(pair, &pair_mask);
4244 + }
4245 + if (pair_mask)
4246 + msleep(250);
4247 + }
4248 +
4249 + *finished = true;
4250 +
4251 + return 0;
4252 +}
4253 +
4254 +static void at803x_cable_test_autoneg(struct phy_device *phydev)
4255 +{
4256 + /* Enable auto-negotiation, but advertise no capabilities, no link
4257 + * will be established. A restart of the auto-negotiation is not
4258 + * required, because the cable test will automatically break the link.
4259 + */
4260 + phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
4261 + phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
4262 +}
4263 +
4264 +static int at803x_cable_test_start(struct phy_device *phydev)
4265 +{
4266 + at803x_cable_test_autoneg(phydev);
4267 + /* we do all the (time consuming) work later */
4268 + return 0;
4269 +}
4270 +
4271 +static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
4272 + unsigned int selector)
4273 +{
4274 + struct phy_device *phydev = rdev_get_drvdata(rdev);
4275 +
4276 + if (selector)
4277 + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
4278 + 0, AT803X_DEBUG_RGMII_1V8);
4279 + else
4280 + return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
4281 + AT803X_DEBUG_RGMII_1V8, 0);
4282 +}
4283 +
4284 +static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
4285 +{
4286 + struct phy_device *phydev = rdev_get_drvdata(rdev);
4287 + int val;
4288 +
4289 + val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
4290 + if (val < 0)
4291 + return val;
4292 +
4293 + return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
4294 +}
4295 +
4296 +static const struct regulator_ops vddio_regulator_ops = {
4297 + .list_voltage = regulator_list_voltage_table,
4298 + .set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
4299 + .get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
4300 +};
4301 +
4302 +static const unsigned int vddio_voltage_table[] = {
4303 + 1500000,
4304 + 1800000,
4305 +};
4306 +
4307 +static const struct regulator_desc vddio_desc = {
4308 + .name = "vddio",
4309 + .of_match = of_match_ptr("vddio-regulator"),
4310 + .n_voltages = ARRAY_SIZE(vddio_voltage_table),
4311 + .volt_table = vddio_voltage_table,
4312 + .ops = &vddio_regulator_ops,
4313 + .type = REGULATOR_VOLTAGE,
4314 + .owner = THIS_MODULE,
4315 +};
4316 +
4317 +static const struct regulator_ops vddh_regulator_ops = {
4318 +};
4319 +
4320 +static const struct regulator_desc vddh_desc = {
4321 + .name = "vddh",
4322 + .of_match = of_match_ptr("vddh-regulator"),
4323 + .n_voltages = 1,
4324 + .fixed_uV = 2500000,
4325 + .ops = &vddh_regulator_ops,
4326 + .type = REGULATOR_VOLTAGE,
4327 + .owner = THIS_MODULE,
4328 +};
4329 +
4330 +static int at8031_register_regulators(struct phy_device *phydev)
4331 +{
4332 + struct at803x_priv *priv = phydev->priv;
4333 + struct device *dev = &phydev->mdio.dev;
4334 + struct regulator_config config = { };
4335 +
4336 + config.dev = dev;
4337 + config.driver_data = phydev;
4338 +
4339 + priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
4340 + if (IS_ERR(priv->vddio_rdev)) {
4341 + phydev_err(phydev, "failed to register VDDIO regulator\n");
4342 + return PTR_ERR(priv->vddio_rdev);
4343 + }
4344 +
4345 + priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
4346 + if (IS_ERR(priv->vddh_rdev)) {
4347 + phydev_err(phydev, "failed to register VDDH regulator\n");
4348 + return PTR_ERR(priv->vddh_rdev);
4349 + }
4350 +
4351 + return 0;
4352 +}
4353 +
4354 +static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
4355 +{
4356 + struct phy_device *phydev = upstream;
4357 + __ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
4358 + __ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
4359 + DECLARE_PHY_INTERFACE_MASK(interfaces);
4360 + phy_interface_t iface;
4361 +
4362 + linkmode_zero(phy_support);
4363 + phylink_set(phy_support, 1000baseX_Full);
4364 + phylink_set(phy_support, 1000baseT_Full);
4365 + phylink_set(phy_support, Autoneg);
4366 + phylink_set(phy_support, Pause);
4367 + phylink_set(phy_support, Asym_Pause);
4368 +
4369 + linkmode_zero(sfp_support);
4370 + sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces);
4371 + /* Some modules support 10G modes as well as others we support.
4372 + * Mask out non-supported modes so the correct interface is picked.
4373 + */
4374 + linkmode_and(sfp_support, phy_support, sfp_support);
4375 +
4376 + if (linkmode_empty(sfp_support)) {
4377 + dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
4378 + return -EINVAL;
4379 + }
4380 +
4381 + iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
4382 +
4383 + /* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
4384 + * interface for use with SFP modules.
4385 + * However, some copper modules detected as having a preferred SGMII
4386 + * interface do default to and function in 1000Base-X mode, so just
4387 + * print a warning and allow such modules, as they may have some chance
4388 + * of working.
4389 + */
4390 + if (iface == PHY_INTERFACE_MODE_SGMII)
4391 + dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
4392 + else if (iface != PHY_INTERFACE_MODE_1000BASEX)
4393 + return -EINVAL;
4394 +
4395 + return 0;
4396 +}
4397 +
4398 +static const struct sfp_upstream_ops at8031_sfp_ops = {
4399 + .attach = phy_sfp_attach,
4400 + .detach = phy_sfp_detach,
4401 + .module_insert = at8031_sfp_insert,
4402 +};
4403 +
4404 +static int at8031_parse_dt(struct phy_device *phydev)
4405 +{
4406 + struct device_node *node = phydev->mdio.dev.of_node;
4407 + struct at803x_priv *priv = phydev->priv;
4408 + int ret;
4409 +
4410 + if (of_property_read_bool(node, "qca,keep-pll-enabled"))
4411 + priv->flags |= AT803X_KEEP_PLL_ENABLED;
4412 +
4413 + ret = at8031_register_regulators(phydev);
4414 + if (ret < 0)
4415 + return ret;
4416 +
4417 + ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
4418 + "vddio");
4419 + if (ret) {
4420 + phydev_err(phydev, "failed to get VDDIO regulator\n");
4421 + return ret;
4422 + }
4423 +
4424 + /* Only AR8031/8033 support 1000Base-X for SFP modules */
4425 + return phy_sfp_probe(phydev, &at8031_sfp_ops);
4426 +}
4427 +
4428 +static int at8031_probe(struct phy_device *phydev)
4429 +{
4430 + struct at803x_priv *priv = phydev->priv;
4431 + int mode_cfg;
4432 + int ccr;
4433 + int ret;
4434 +
4435 + ret = at803x_probe(phydev);
4436 + if (ret)
4437 + return ret;
4438 +
4439 + /* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
4440 + * options.
4441 + */
4442 + ret = at8031_parse_dt(phydev);
4443 + if (ret)
4444 + return ret;
4445 +
4446 + ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
4447 + if (ccr < 0)
4448 + return ccr;
4449 + mode_cfg = ccr & AT803X_MODE_CFG_MASK;
4450 +
4451 + switch (mode_cfg) {
4452 + case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
4453 + case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
4454 + priv->is_1000basex = true;
4455 + fallthrough;
4456 + case AT803X_MODE_CFG_FX100_RGMII_50OHM:
4457 + case AT803X_MODE_CFG_FX100_RGMII_75OHM:
4458 + priv->is_fiber = true;
4459 + break;
4460 + }
4461 +
4462 + /* Disable WoL in 1588 register which is enabled
4463 + * by default
4464 + */
4465 + return phy_modify_mmd(phydev, MDIO_MMD_PCS,
4466 + AT803X_PHY_MMD3_WOL_CTRL,
4467 + AT803X_WOL_EN, 0);
4468 +}
4469 +
4470 +static int at8031_config_init(struct phy_device *phydev)
4471 +{
4472 + struct at803x_priv *priv = phydev->priv;
4473 + int ret;
4474 +
4475 + /* Some bootloaders leave the fiber page selected.
4476 + * Switch to the appropriate page (fiber or copper), as otherwise we
4477 + * read the PHY capabilities from the wrong page.
4478 + */
4479 + phy_lock_mdio_bus(phydev);
4480 + ret = at803x_write_page(phydev,
4481 + priv->is_fiber ? AT803X_PAGE_FIBER :
4482 + AT803X_PAGE_COPPER);
4483 + phy_unlock_mdio_bus(phydev);
4484 + if (ret)
4485 + return ret;
4486 +
4487 + ret = at8031_pll_config(phydev);
4488 + if (ret < 0)
4489 + return ret;
4490 +
4491 + return at803x_config_init(phydev);
4492 +}
4493 +
4494 +static int at8031_set_wol(struct phy_device *phydev,
4495 + struct ethtool_wolinfo *wol)
4496 +{
4497 + int ret;
4498 +
4499 + /* First setup MAC address and enable WOL interrupt */
4500 + ret = at803x_set_wol(phydev, wol);
4501 + if (ret)
4502 + return ret;
4503 +
4504 + if (wol->wolopts & WAKE_MAGIC)
4505 + /* Enable WOL function for 1588 */
4506 + ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
4507 + AT803X_PHY_MMD3_WOL_CTRL,
4508 + 0, AT803X_WOL_EN);
4509 + else
4510 + /* Disable WoL function for 1588 */
4511 + ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
4512 + AT803X_PHY_MMD3_WOL_CTRL,
4513 + AT803X_WOL_EN, 0);
4514 +
4515 + return ret;
4516 +}
4517 +
4518 +static int at8031_config_intr(struct phy_device *phydev)
4519 +{
4520 + struct at803x_priv *priv = phydev->priv;
4521 + int err, value = 0;
4522 +
4523 + if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
4524 + priv->is_fiber) {
4525 + /* Clear any pending interrupts */
4526 + err = at803x_ack_interrupt(phydev);
4527 + if (err)
4528 + return err;
4529 +
4530 + value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
4531 + value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
4532 +
4533 + err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);
4534 + if (err)
4535 + return err;
4536 + }
4537 +
4538 + return at803x_config_intr(phydev);
4539 +}
4540 +
4541 +/* AR8031 and AR8033 share the same read status logic */
4542 +static int at8031_read_status(struct phy_device *phydev)
4543 +{
4544 + struct at803x_priv *priv = phydev->priv;
4545 +
4546 + if (priv->is_1000basex)
4547 + return genphy_c37_read_status(phydev);
4548 +
4549 + return at803x_read_status(phydev);
4550 +}
4551 +
4552 +/* AR8031 and AR8035 share the same cable test get status reg */
4553 +static int at8031_cable_test_get_status(struct phy_device *phydev,
4554 + bool *finished)
4555 +{
4556 + return at803x_cable_test_get_status(phydev, finished, 0xf);
4557 +}
4558 +
4559 +/* AR8031 and AR8035 share the same cable test start logic */
4560 +static int at8031_cable_test_start(struct phy_device *phydev)
4561 +{
4562 + at803x_cable_test_autoneg(phydev);
4563 + phy_write(phydev, MII_CTRL1000, 0);
4564 + /* we do all the (time consuming) work later */
4565 + return 0;
4566 +}
4567 +
4568 +/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
4569 +static int at8032_cable_test_get_status(struct phy_device *phydev,
4570 + bool *finished)
4571 +{
4572 + return at803x_cable_test_get_status(phydev, finished, 0x3);
4573 +}
4574 +
4575 +static int at8035_parse_dt(struct phy_device *phydev)
4576 +{
4577 + struct at803x_priv *priv = phydev->priv;
4578 +
4579 + /* Mask is set by the generic at803x_parse_dt
4580 + * if property is set. Assume property is set
4581 + * with the mask not zero.
4582 + */
4583 + if (priv->clk_25m_mask) {
4584 + /* Fixup for the AR8030/AR8035. This chip has another mask and
4585 + * doesn't support the DSP reference. Eg. the lowest bit of the
4586 + * mask. The upper two bits select the same frequencies. Mask
4587 + * the lowest bit here.
4588 + *
4589 + * Warning:
4590 + * There was no datasheet for the AR8030 available so this is
4591 + * just a guess. But the AR8035 is listed as pin compatible
4592 + * to the AR8030 so there might be a good chance it works on
4593 + * the AR8030 too.
4594 + */
4595 + priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
4596 + priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
4597 + }
4598 +
4599 + return 0;
4600 +}
4601 +
4602 +/* AR8030 and AR8035 shared the same special mask for clk_25m */
4603 +static int at8035_probe(struct phy_device *phydev)
4604 +{
4605 + int ret;
4606 +
4607 + ret = at803x_probe(phydev);
4608 + if (ret)
4609 + return ret;
4610 +
4611 + return at8035_parse_dt(phydev);
4612 +}
4613 +
4614 +static int qca83xx_config_init(struct phy_device *phydev)
4615 +{
4616 + u8 switch_revision;
4617 +
4618 + switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
4619 +
4620 + switch (switch_revision) {
4621 + case 1:
4622 + /* For 100M waveform */
4623 + at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
4624 + /* Turn on Gigabit clock */
4625 + at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
4626 + break;
4627 +
4628 + case 2:
4629 + phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
4630 + fallthrough;
4631 + case 4:
4632 + phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
4633 + at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
4634 + at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
4635 + at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
4636 + break;
4637 + }
4638 +
4639 + /* Following original QCA sourcecode set port to prefer master */
4640 + phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
4641 +
4642 + return 0;
4643 +}
4644 +
4645 +static int qca8327_config_init(struct phy_device *phydev)
4646 +{
4647 + /* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
4648 + * Disable on init and enable only with 100m speed following
4649 + * qca original source code.
4650 + */
4651 + at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
4652 + QCA8327_DEBUG_MANU_CTRL_EN, 0);
4653 +
4654 + return qca83xx_config_init(phydev);
4655 +}
4656 +
4657 +static void qca83xx_link_change_notify(struct phy_device *phydev)
4658 +{
4659 + /* Set DAC Amplitude adjustment to +6% for 100m on link running */
4660 + if (phydev->state == PHY_RUNNING) {
4661 + if (phydev->speed == SPEED_100)
4662 + at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
4663 + QCA8327_DEBUG_MANU_CTRL_EN,
4664 + QCA8327_DEBUG_MANU_CTRL_EN);
4665 + } else {
4666 + /* Reset DAC Amplitude adjustment */
4667 + at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
4668 + QCA8327_DEBUG_MANU_CTRL_EN, 0);
4669 + }
4670 +}
4671 +
4672 +static int qca83xx_resume(struct phy_device *phydev)
4673 +{
4674 + int ret, val;
4675 +
4676 + /* Skip reset if not suspended */
4677 + if (!phydev->suspended)
4678 + return 0;
4679 +
4680 + /* Reinit the port, reset values set by suspend */
4681 + qca83xx_config_init(phydev);
4682 +
4683 + /* Reset the port on port resume */
4684 + phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
4685 +
4686 + /* On resume from suspend the switch execute a reset and
4687 + * restart auto-negotiation. Wait for reset to complete.
4688 + */
4689 + ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
4690 + 50000, 600000, true);
4691 + if (ret)
4692 + return ret;
4693 +
4694 + usleep_range(1000, 2000);
4695 +
4696 + return 0;
4697 +}
4698 +
4699 +static int qca83xx_suspend(struct phy_device *phydev)
4700 +{
4701 + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
4702 + AT803X_DEBUG_GATE_CLK_IN1000, 0);
4703 +
4704 + at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
4705 + AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
4706 + AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
4707 +
4708 + return 0;
4709 +}
4710 +
4711 +static int qca8337_suspend(struct phy_device *phydev)
4712 +{
4713 + /* Only QCA8337 support actual suspend. */
4714 + genphy_suspend(phydev);
4715 +
4716 + return qca83xx_suspend(phydev);
4717 +}
4718 +
4719 +static int qca8327_suspend(struct phy_device *phydev)
4720 +{
4721 + u16 mask = 0;
4722 +
4723 + /* QCA8327 cause port unreliability when phy suspend
4724 + * is set.
4725 + */
4726 + mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
4727 + phy_modify(phydev, MII_BMCR, mask, 0);
4728 +
4729 + return qca83xx_suspend(phydev);
4730 +}
4731 +
4732 +static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
4733 +{
4734 + int ret;
4735 +
4736 + /* Enable fast retrain */
4737 + ret = genphy_c45_fast_retrain(phydev, true);
4738 + if (ret)
4739 + return ret;
4740 +
4741 + phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
4742 + QCA808X_TOP_OPTION1_DATA);
4743 + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
4744 + QCA808X_MSE_THRESHOLD_20DB_VALUE);
4745 + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
4746 + QCA808X_MSE_THRESHOLD_17DB_VALUE);
4747 + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
4748 + QCA808X_MSE_THRESHOLD_27DB_VALUE);
4749 + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
4750 + QCA808X_MSE_THRESHOLD_28DB_VALUE);
4751 + phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
4752 + QCA808X_MMD3_DEBUG_1_VALUE);
4753 + phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
4754 + QCA808X_MMD3_DEBUG_4_VALUE);
4755 + phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
4756 + QCA808X_MMD3_DEBUG_5_VALUE);
4757 + phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
4758 + QCA808X_MMD3_DEBUG_3_VALUE);
4759 + phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
4760 + QCA808X_MMD3_DEBUG_6_VALUE);
4761 + phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
4762 + QCA808X_MMD3_DEBUG_2_VALUE);
4763 +
4764 + return 0;
4765 +}
4766 +
4767 +static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
4768 +{
4769 + u16 seed_value;
4770 +
4771 + if (!enable)
4772 + return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
4773 + QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
4774 +
4775 + seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE);
4776 + return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
4777 + QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
4778 + FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
4779 + QCA808X_MASTER_SLAVE_SEED_ENABLE);
4780 +}
4781 +
4782 +static bool qca808x_is_prefer_master(struct phy_device *phydev)
4783 +{
4784 + return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
4785 + (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
4786 +}
4787 +
4788 +static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
4789 +{
4790 + return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
4791 +}
4792 +
4793 +static int qca808x_config_init(struct phy_device *phydev)
4794 +{
4795 + int ret;
4796 +
4797 + /* Active adc&vga on 802.3az for the link 1000M and 100M */
4798 + ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
4799 + QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
4800 + if (ret)
4801 + return ret;
4802 +
4803 + /* Adjust the threshold on 802.3az for the link 1000M */
4804 + ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
4805 + QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
4806 + QCA808X_MMD3_AZ_TRAINING_VAL);
4807 + if (ret)
4808 + return ret;
4809 +
4810 + if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
4811 + /* Config the fast retrain for the link 2500M */
4812 + ret = qca808x_phy_fast_retrain_config(phydev);
4813 + if (ret)
4814 + return ret;
4815 +
4816 + ret = genphy_read_master_slave(phydev);
4817 + if (ret < 0)
4818 + return ret;
4819 +
4820 + if (!qca808x_is_prefer_master(phydev)) {
4821 + /* Enable seed and configure lower ramdom seed to make phy
4822 + * linked as slave mode.
4823 + */
4824 + ret = qca808x_phy_ms_seed_enable(phydev, true);
4825 + if (ret)
4826 + return ret;
4827 + }
4828 + }
4829 +
4830 + /* Configure adc threshold as 100mv for the link 10M */
4831 + return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
4832 + QCA808X_ADC_THRESHOLD_MASK,
4833 + QCA808X_ADC_THRESHOLD_100MV);
4834 +}
4835 +
4836 +static int qca808x_read_status(struct phy_device *phydev)
4837 +{
4838 + struct at803x_ss_mask ss_mask = { 0 };
4839 + int ret;
4840 +
4841 + ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
4842 + if (ret < 0)
4843 + return ret;
4844 +
4845 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
4846 + ret & MDIO_AN_10GBT_STAT_LP2_5G);
4847 +
4848 + ret = genphy_read_status(phydev);
4849 + if (ret)
4850 + return ret;
4851 +
4852 + /* qca8081 takes the different bits for speed value from at803x */
4853 + ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
4854 + ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
4855 + ret = at803x_read_specific_status(phydev, ss_mask);
4856 + if (ret < 0)
4857 + return ret;
4858 +
4859 + if (phydev->link) {
4860 + if (phydev->speed == SPEED_2500)
4861 + phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
4862 + else
4863 + phydev->interface = PHY_INTERFACE_MODE_SGMII;
4864 + } else {
4865 + /* generate seed as a lower random value to make PHY linked as SLAVE easily,
4866 + * except for master/slave configuration fault detected or the master mode
4867 + * preferred.
4868 + *
4869 + * the reason for not putting this code into the function link_change_notify is
4870 + * the corner case where the link partner is also the qca8081 PHY and the seed
4871 + * value is configured as the same value, the link can't be up and no link change
4872 + * occurs.
4873 + */
4874 + if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
4875 + if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
4876 + qca808x_is_prefer_master(phydev)) {
4877 + qca808x_phy_ms_seed_enable(phydev, false);
4878 + } else {
4879 + qca808x_phy_ms_seed_enable(phydev, true);
4880 + }
4881 + }
4882 + }
4883 +
4884 + return 0;
4885 +}
4886 +
4887 +static int qca808x_soft_reset(struct phy_device *phydev)
4888 +{
4889 + int ret;
4890 +
4891 + ret = genphy_soft_reset(phydev);
4892 + if (ret < 0)
4893 + return ret;
4894 +
4895 + if (qca808x_has_fast_retrain_or_slave_seed(phydev))
4896 + ret = qca808x_phy_ms_seed_enable(phydev, true);
4897 +
4898 + return ret;
4899 +}
4900 +
4901 +static bool qca808x_cdt_fault_length_valid(int cdt_code)
4902 +{
4903 + switch (cdt_code) {
4904 + case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
4905 + case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
4906 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
4907 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
4908 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
4909 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
4910 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
4911 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
4912 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
4913 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
4914 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
4915 + return true;
4916 + default:
4917 + return false;
4918 + }
4919 +}
4920 +
4921 +static int qca808x_cable_test_result_trans(int cdt_code)
4922 +{
4923 + switch (cdt_code) {
4924 + case QCA808X_CDT_STATUS_STAT_NORMAL:
4925 + return ETHTOOL_A_CABLE_RESULT_CODE_OK;
4926 + case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
4927 + return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
4928 + case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
4929 + return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
4930 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
4931 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
4932 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
4933 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
4934 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
4935 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
4936 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
4937 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
4938 + case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
4939 + return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
4940 + case QCA808X_CDT_STATUS_STAT_FAIL:
4941 + default:
4942 + return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
4943 + }
4944 +}
4945 +
4946 +static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
4947 + int result)
4948 +{
4949 + int val;
4950 + u32 cdt_length_reg = 0;
4951 +
4952 + switch (pair) {
4953 + case ETHTOOL_A_CABLE_PAIR_A:
4954 + cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
4955 + break;
4956 + case ETHTOOL_A_CABLE_PAIR_B:
4957 + cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
4958 + break;
4959 + case ETHTOOL_A_CABLE_PAIR_C:
4960 + cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
4961 + break;
4962 + case ETHTOOL_A_CABLE_PAIR_D:
4963 + cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
4964 + break;
4965 + default:
4966 + return -EINVAL;
4967 + }
4968 +
4969 + val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
4970 + if (val < 0)
4971 + return val;
4972 +
4973 + if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
4974 + val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
4975 + else
4976 + val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
4977 +
4978 + return at803x_cdt_fault_length(val);
4979 +}
4980 +
4981 +static int qca808x_cable_test_start(struct phy_device *phydev)
4982 +{
4983 + int ret;
4984 +
4985 + /* perform CDT with the following configs:
4986 + * 1. disable hibernation.
4987 + * 2. force PHY working in MDI mode.
4988 + * 3. for PHY working in 1000BaseT.
4989 + * 4. configure the threshold.
4990 + */
4991 +
4992 + ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
4993 + if (ret < 0)
4994 + return ret;
4995 +
4996 + ret = at803x_config_mdix(phydev, ETH_TP_MDI);
4997 + if (ret < 0)
4998 + return ret;
4999 +
5000 + /* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
5001 + phydev->duplex = DUPLEX_FULL;
5002 + phydev->speed = SPEED_1000;
5003 + ret = genphy_c45_pma_setup_forced(phydev);
5004 + if (ret < 0)
5005 + return ret;
5006 +
5007 + ret = genphy_setup_forced(phydev);
5008 + if (ret < 0)
5009 + return ret;
5010 +
5011 + /* configure the thresholds for open, short, pair ok test */
5012 + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
5013 + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
5014 + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
5015 + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
5016 + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
5017 + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
5018 +
5019 + return 0;
5020 +}
5021 +
5022 +static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
5023 + u16 status)
5024 +{
5025 + int length, result;
5026 + u16 pair_code;
5027 +
5028 + switch (pair) {
5029 + case ETHTOOL_A_CABLE_PAIR_A:
5030 + pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
5031 + break;
5032 + case ETHTOOL_A_CABLE_PAIR_B:
5033 + pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
5034 + break;
5035 + case ETHTOOL_A_CABLE_PAIR_C:
5036 + pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
5037 + break;
5038 + case ETHTOOL_A_CABLE_PAIR_D:
5039 + pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
5040 + break;
5041 + default:
5042 + return -EINVAL;
5043 + }
5044 +
5045 + result = qca808x_cable_test_result_trans(pair_code);
5046 + ethnl_cable_test_result(phydev, pair, result);
5047 +
5048 + if (qca808x_cdt_fault_length_valid(pair_code)) {
5049 + length = qca808x_cdt_fault_length(phydev, pair, result);
5050 + ethnl_cable_test_fault_length(phydev, pair, length);
5051 + }
5052 +
5053 + return 0;
5054 +}
5055 +
5056 +static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
5057 +{
5058 + int ret, val;
5059 +
5060 + *finished = false;
5061 +
5062 + val = QCA808X_CDT_ENABLE_TEST |
5063 + QCA808X_CDT_LENGTH_UNIT;
5064 + ret = at803x_cdt_start(phydev, val);
5065 + if (ret)
5066 + return ret;
5067 +
5068 + ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
5069 + if (ret)
5070 + return ret;
5071 +
5072 + val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
5073 + if (val < 0)
5074 + return val;
5075 +
5076 + ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
5077 + if (ret)
5078 + return ret;
5079 +
5080 + ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
5081 + if (ret)
5082 + return ret;
5083 +
5084 + ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
5085 + if (ret)
5086 + return ret;
5087 +
5088 + ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
5089 + if (ret)
5090 + return ret;
5091 +
5092 + *finished = true;
5093 +
5094 + return 0;
5095 +}
5096 +
5097 +static int qca808x_get_features(struct phy_device *phydev)
5098 +{
5099 + int ret;
5100 +
5101 + ret = genphy_c45_pma_read_abilities(phydev);
5102 + if (ret)
5103 + return ret;
5104 +
5105 + /* The autoneg ability is not existed in bit3 of MMD7.1,
5106 + * but it is supported by qca808x PHY, so we add it here
5107 + * manually.
5108 + */
5109 + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
5110 +
5111 + /* As for the qca8081 1G version chip, the 2500baseT ability is also
5112 + * existed in the bit0 of MMD1.21, we need to remove it manually if
5113 + * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
5114 + */
5115 + ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
5116 + if (ret < 0)
5117 + return ret;
5118 +
5119 + if (QCA808X_PHY_CHIP_TYPE_1G & ret)
5120 + linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
5121 +
5122 + return 0;
5123 +}
5124 +
5125 +static int qca808x_config_aneg(struct phy_device *phydev)
5126 +{
5127 + int phy_ctrl = 0;
5128 + int ret;
5129 +
5130 + ret = at803x_prepare_config_aneg(phydev);
5131 + if (ret)
5132 + return ret;
5133 +
5134 + /* The reg MII_BMCR also needs to be configured for force mode, the
5135 + * genphy_config_aneg is also needed.
5136 + */
5137 + if (phydev->autoneg == AUTONEG_DISABLE)
5138 + genphy_c45_pma_setup_forced(phydev);
5139 +
5140 + if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
5141 + phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
5142 +
5143 + ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
5144 + MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
5145 + if (ret < 0)
5146 + return ret;
5147 +
5148 + return __genphy_config_aneg(phydev, ret);
5149 +}
5150 +
5151 +static void qca808x_link_change_notify(struct phy_device *phydev)
5152 +{
5153 + /* Assert interface sgmii fifo on link down, deassert it on link up,
5154 + * the interface device address is always phy address added by 1.
5155 + */
5156 + mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
5157 + MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
5158 + QCA8081_PHY_FIFO_RSTN,
5159 + phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
5160 +}
5161 +
5162 +static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
5163 + u16 *offload_trigger)
5164 +{
5165 + /* Parsing specific to netdev trigger */
5166 + if (test_bit(TRIGGER_NETDEV_TX, &rules))
5167 + *offload_trigger |= QCA808X_LED_TX_BLINK;
5168 + if (test_bit(TRIGGER_NETDEV_RX, &rules))
5169 + *offload_trigger |= QCA808X_LED_RX_BLINK;
5170 + if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
5171 + *offload_trigger |= QCA808X_LED_SPEED10_ON;
5172 + if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
5173 + *offload_trigger |= QCA808X_LED_SPEED100_ON;
5174 + if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
5175 + *offload_trigger |= QCA808X_LED_SPEED1000_ON;
5176 + if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
5177 + *offload_trigger |= QCA808X_LED_SPEED2500_ON;
5178 + if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
5179 + *offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
5180 + if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
5181 + *offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
5182 +
5183 + if (rules && !*offload_trigger)
5184 + return -EOPNOTSUPP;
5185 +
5186 + /* Enable BLINK_CHECK_BYPASS by default to make the LED
5187 + * blink even with duplex or speed mode not enabled.
5188 + */
5189 + *offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
5190 +
5191 + return 0;
5192 +}
5193 +
5194 +static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
5195 +{
5196 + u16 reg;
5197 +
5198 + if (index > 2)
5199 + return -EINVAL;
5200 +
5201 + reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
5202 +
5203 + return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
5204 + QCA808X_LED_FORCE_EN);
5205 +}
5206 +
5207 +static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
5208 + unsigned long rules)
5209 +{
5210 + u16 offload_trigger = 0;
5211 +
5212 + if (index > 2)
5213 + return -EINVAL;
5214 +
5215 + return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
5216 +}
5217 +
5218 +static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
5219 + unsigned long rules)
5220 +{
5221 + u16 reg, offload_trigger = 0;
5222 + int ret;
5223 +
5224 + if (index > 2)
5225 + return -EINVAL;
5226 +
5227 + reg = QCA808X_MMD7_LED_CTRL(index);
5228 +
5229 + ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
5230 + if (ret)
5231 + return ret;
5232 +
5233 + ret = qca808x_led_hw_control_enable(phydev, index);
5234 + if (ret)
5235 + return ret;
5236 +
5237 + return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
5238 + QCA808X_LED_PATTERN_MASK,
5239 + offload_trigger);
5240 +}
5241 +
5242 +static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
5243 +{
5244 + u16 reg;
5245 + int val;
5246 +
5247 + if (index > 2)
5248 + return false;
5249 +
5250 + reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
5251 +
5252 + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
5253 +
5254 + return !(val & QCA808X_LED_FORCE_EN);
5255 +}
5256 +
5257 +static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
5258 + unsigned long *rules)
5259 +{
5260 + u16 reg;
5261 + int val;
5262 +
5263 + if (index > 2)
5264 + return -EINVAL;
5265 +
5266 + /* Check if we have hw control enabled */
5267 + if (qca808x_led_hw_control_status(phydev, index))
5268 + return -EINVAL;
5269 +
5270 + reg = QCA808X_MMD7_LED_CTRL(index);
5271 +
5272 + val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
5273 + if (val & QCA808X_LED_TX_BLINK)
5274 + set_bit(TRIGGER_NETDEV_TX, rules);
5275 + if (val & QCA808X_LED_RX_BLINK)
5276 + set_bit(TRIGGER_NETDEV_RX, rules);
5277 + if (val & QCA808X_LED_SPEED10_ON)
5278 + set_bit(TRIGGER_NETDEV_LINK_10, rules);
5279 + if (val & QCA808X_LED_SPEED100_ON)
5280 + set_bit(TRIGGER_NETDEV_LINK_100, rules);
5281 + if (val & QCA808X_LED_SPEED1000_ON)
5282 + set_bit(TRIGGER_NETDEV_LINK_1000, rules);
5283 + if (val & QCA808X_LED_SPEED2500_ON)
5284 + set_bit(TRIGGER_NETDEV_LINK_2500, rules);
5285 + if (val & QCA808X_LED_HALF_DUPLEX_ON)
5286 + set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
5287 + if (val & QCA808X_LED_FULL_DUPLEX_ON)
5288 + set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
5289 +
5290 + return 0;
5291 +}
5292 +
5293 +static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
5294 +{
5295 + u16 reg;
5296 +
5297 + if (index > 2)
5298 + return -EINVAL;
5299 +
5300 + reg = QCA808X_MMD7_LED_CTRL(index);
5301 +
5302 + return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
5303 + QCA808X_LED_PATTERN_MASK);
5304 +}
5305 +
5306 +static int qca808x_led_brightness_set(struct phy_device *phydev,
5307 + u8 index, enum led_brightness value)
5308 +{
5309 + u16 reg;
5310 + int ret;
5311 +
5312 + if (index > 2)
5313 + return -EINVAL;
5314 +
5315 + if (!value) {
5316 + ret = qca808x_led_hw_control_reset(phydev, index);
5317 + if (ret)
5318 + return ret;
5319 + }
5320 +
5321 + reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
5322 +
5323 + return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
5324 + QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
5325 + QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
5326 + QCA808X_LED_FORCE_OFF);
5327 +}
5328 +
5329 +static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
5330 + unsigned long *delay_on,
5331 + unsigned long *delay_off)
5332 +{
5333 + int ret;
5334 + u16 reg;
5335 +
5336 + if (index > 2)
5337 + return -EINVAL;
5338 +
5339 + reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
5340 +
5341 + /* Set blink to 50% off, 50% on at 4Hz by default */
5342 + ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
5343 + QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
5344 + QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
5345 + if (ret)
5346 + return ret;
5347 +
5348 + /* We use BLINK_1 for normal blinking */
5349 + ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
5350 + QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
5351 + QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
5352 + if (ret)
5353 + return ret;
5354 +
5355 + /* We set blink to 4Hz, aka 250ms */
5356 + *delay_on = 250 / 2;
5357 + *delay_off = 250 / 2;
5358 +
5359 + return 0;
5360 +}
5361 +
5362 +static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
5363 + unsigned long modes)
5364 +{
5365 + struct at803x_priv *priv = phydev->priv;
5366 + bool active_low = false;
5367 + u32 mode;
5368 +
5369 + for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
5370 + switch (mode) {
5371 + case PHY_LED_ACTIVE_LOW:
5372 + active_low = true;
5373 + break;
5374 + default:
5375 + return -EINVAL;
5376 + }
5377 + }
5378 +
5379 + /* PHY polarity is global and can't be set per LED.
5380 + * To detect this, check if last requested polarity mode
5381 + * match the new one.
5382 + */
5383 + if (priv->led_polarity_mode >= 0 &&
5384 + priv->led_polarity_mode != active_low) {
5385 + phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
5386 + return -EINVAL;
5387 + }
5388 +
5389 + /* Save the last PHY polarity mode */
5390 + priv->led_polarity_mode = active_low;
5391 +
5392 + return phy_modify_mmd(phydev, MDIO_MMD_AN,
5393 + QCA808X_MMD7_LED_POLARITY_CTRL,
5394 + QCA808X_LED_ACTIVE_HIGH,
5395 + active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
5396 +}
5397 +
5398 +static struct phy_driver at803x_driver[] = {
5399 +{
5400 + /* Qualcomm Atheros AR8035 */
5401 + PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
5402 + .name = "Qualcomm Atheros AR8035",
5403 + .flags = PHY_POLL_CABLE_TEST,
5404 + .probe = at8035_probe,
5405 + .config_aneg = at803x_config_aneg,
5406 + .config_init = at803x_config_init,
5407 + .soft_reset = genphy_soft_reset,
5408 + .set_wol = at803x_set_wol,
5409 + .get_wol = at803x_get_wol,
5410 + .suspend = at803x_suspend,
5411 + .resume = at803x_resume,
5412 + /* PHY_GBIT_FEATURES */
5413 + .read_status = at803x_read_status,
5414 + .config_intr = at803x_config_intr,
5415 + .handle_interrupt = at803x_handle_interrupt,
5416 + .get_tunable = at803x_get_tunable,
5417 + .set_tunable = at803x_set_tunable,
5418 + .cable_test_start = at8031_cable_test_start,
5419 + .cable_test_get_status = at8031_cable_test_get_status,
5420 +}, {
5421 + /* Qualcomm Atheros AR8030 */
5422 + .phy_id = ATH8030_PHY_ID,
5423 + .name = "Qualcomm Atheros AR8030",
5424 + .phy_id_mask = AT8030_PHY_ID_MASK,
5425 + .probe = at8035_probe,
5426 + .config_init = at803x_config_init,
5427 + .link_change_notify = at803x_link_change_notify,
5428 + .set_wol = at803x_set_wol,
5429 + .get_wol = at803x_get_wol,
5430 + .suspend = at803x_suspend,
5431 + .resume = at803x_resume,
5432 + /* PHY_BASIC_FEATURES */
5433 + .config_intr = at803x_config_intr,
5434 + .handle_interrupt = at803x_handle_interrupt,
5435 +}, {
5436 + /* Qualcomm Atheros AR8031/AR8033 */
5437 + PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
5438 + .name = "Qualcomm Atheros AR8031/AR8033",
5439 + .flags = PHY_POLL_CABLE_TEST,
5440 + .probe = at8031_probe,
5441 + .config_init = at8031_config_init,
5442 + .config_aneg = at803x_config_aneg,
5443 + .soft_reset = genphy_soft_reset,
5444 + .set_wol = at8031_set_wol,
5445 + .get_wol = at803x_get_wol,
5446 + .suspend = at803x_suspend,
5447 + .resume = at803x_resume,
5448 + .read_page = at803x_read_page,
5449 + .write_page = at803x_write_page,
5450 + .get_features = at803x_get_features,
5451 + .read_status = at8031_read_status,
5452 + .config_intr = at8031_config_intr,
5453 + .handle_interrupt = at803x_handle_interrupt,
5454 + .get_tunable = at803x_get_tunable,
5455 + .set_tunable = at803x_set_tunable,
5456 + .cable_test_start = at8031_cable_test_start,
5457 + .cable_test_get_status = at8031_cable_test_get_status,
5458 +}, {
5459 + /* Qualcomm Atheros AR8032 */
5460 + PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
5461 + .name = "Qualcomm Atheros AR8032",
5462 + .probe = at803x_probe,
5463 + .flags = PHY_POLL_CABLE_TEST,
5464 + .config_init = at803x_config_init,
5465 + .link_change_notify = at803x_link_change_notify,
5466 + .suspend = at803x_suspend,
5467 + .resume = at803x_resume,
5468 + /* PHY_BASIC_FEATURES */
5469 + .config_intr = at803x_config_intr,
5470 + .handle_interrupt = at803x_handle_interrupt,
5471 + .cable_test_start = at803x_cable_test_start,
5472 + .cable_test_get_status = at8032_cable_test_get_status,
5473 +}, {
5474 + /* ATHEROS AR9331 */
5475 + PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
5476 + .name = "Qualcomm Atheros AR9331 built-in PHY",
5477 + .probe = at803x_probe,
5478 + .suspend = at803x_suspend,
5479 + .resume = at803x_resume,
5480 + .flags = PHY_POLL_CABLE_TEST,
5481 + /* PHY_BASIC_FEATURES */
5482 + .config_intr = at803x_config_intr,
5483 + .handle_interrupt = at803x_handle_interrupt,
5484 + .cable_test_start = at803x_cable_test_start,
5485 + .cable_test_get_status = at8032_cable_test_get_status,
5486 + .read_status = at803x_read_status,
5487 + .soft_reset = genphy_soft_reset,
5488 + .config_aneg = at803x_config_aneg,
5489 +}, {
5490 + /* Qualcomm Atheros QCA9561 */
5491 + PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
5492 + .name = "Qualcomm Atheros QCA9561 built-in PHY",
5493 + .probe = at803x_probe,
5494 + .suspend = at803x_suspend,
5495 + .resume = at803x_resume,
5496 + .flags = PHY_POLL_CABLE_TEST,
5497 + /* PHY_BASIC_FEATURES */
5498 + .config_intr = at803x_config_intr,
5499 + .handle_interrupt = at803x_handle_interrupt,
5500 + .cable_test_start = at803x_cable_test_start,
5501 + .cable_test_get_status = at8032_cable_test_get_status,
5502 + .read_status = at803x_read_status,
5503 + .soft_reset = genphy_soft_reset,
5504 + .config_aneg = at803x_config_aneg,
5505 +}, {
5506 + /* QCA8337 */
5507 + .phy_id = QCA8337_PHY_ID,
5508 + .phy_id_mask = QCA8K_PHY_ID_MASK,
5509 + .name = "Qualcomm Atheros 8337 internal PHY",
5510 + /* PHY_GBIT_FEATURES */
5511 + .probe = at803x_probe,
5512 + .flags = PHY_IS_INTERNAL,
5513 + .config_init = qca83xx_config_init,
5514 + .soft_reset = genphy_soft_reset,
5515 + .get_sset_count = qca83xx_get_sset_count,
5516 + .get_strings = qca83xx_get_strings,
5517 + .get_stats = qca83xx_get_stats,
5518 + .suspend = qca8337_suspend,
5519 + .resume = qca83xx_resume,
5520 +}, {
5521 + /* QCA8327-A from switch QCA8327-AL1A */
5522 + .phy_id = QCA8327_A_PHY_ID,
5523 + .phy_id_mask = QCA8K_PHY_ID_MASK,
5524 + .name = "Qualcomm Atheros 8327-A internal PHY",
5525 + /* PHY_GBIT_FEATURES */
5526 + .link_change_notify = qca83xx_link_change_notify,
5527 + .probe = at803x_probe,
5528 + .flags = PHY_IS_INTERNAL,
5529 + .config_init = qca8327_config_init,
5530 + .soft_reset = genphy_soft_reset,
5531 + .get_sset_count = qca83xx_get_sset_count,
5532 + .get_strings = qca83xx_get_strings,
5533 + .get_stats = qca83xx_get_stats,
5534 + .suspend = qca8327_suspend,
5535 + .resume = qca83xx_resume,
5536 +}, {
5537 + /* QCA8327-B from switch QCA8327-BL1A */
5538 + .phy_id = QCA8327_B_PHY_ID,
5539 + .phy_id_mask = QCA8K_PHY_ID_MASK,
5540 + .name = "Qualcomm Atheros 8327-B internal PHY",
5541 + /* PHY_GBIT_FEATURES */
5542 + .link_change_notify = qca83xx_link_change_notify,
5543 + .probe = at803x_probe,
5544 + .flags = PHY_IS_INTERNAL,
5545 + .config_init = qca8327_config_init,
5546 + .soft_reset = genphy_soft_reset,
5547 + .get_sset_count = qca83xx_get_sset_count,
5548 + .get_strings = qca83xx_get_strings,
5549 + .get_stats = qca83xx_get_stats,
5550 + .suspend = qca8327_suspend,
5551 + .resume = qca83xx_resume,
5552 +}, {
5553 + /* Qualcomm QCA8081 */
5554 + PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
5555 + .name = "Qualcomm QCA8081",
5556 + .flags = PHY_POLL_CABLE_TEST,
5557 + .probe = at803x_probe,
5558 + .config_intr = at803x_config_intr,
5559 + .handle_interrupt = at803x_handle_interrupt,
5560 + .get_tunable = at803x_get_tunable,
5561 + .set_tunable = at803x_set_tunable,
5562 + .set_wol = at803x_set_wol,
5563 + .get_wol = at803x_get_wol,
5564 + .get_features = qca808x_get_features,
5565 + .config_aneg = qca808x_config_aneg,
5566 + .suspend = genphy_suspend,
5567 + .resume = genphy_resume,
5568 + .read_status = qca808x_read_status,
5569 + .config_init = qca808x_config_init,
5570 + .soft_reset = qca808x_soft_reset,
5571 + .cable_test_start = qca808x_cable_test_start,
5572 + .cable_test_get_status = qca808x_cable_test_get_status,
5573 + .link_change_notify = qca808x_link_change_notify,
5574 + .led_brightness_set = qca808x_led_brightness_set,
5575 + .led_blink_set = qca808x_led_blink_set,
5576 + .led_hw_is_supported = qca808x_led_hw_is_supported,
5577 + .led_hw_control_set = qca808x_led_hw_control_set,
5578 + .led_hw_control_get = qca808x_led_hw_control_get,
5579 + .led_polarity_set = qca808x_led_polarity_set,
5580 +}, };
5581 +
5582 +module_phy_driver(at803x_driver);
5583 +
5584 +static struct mdio_device_id __maybe_unused atheros_tbl[] = {
5585 + { ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
5586 + { PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
5587 + { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
5588 + { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
5589 + { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
5590 + { PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
5591 + { PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
5592 + { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
5593 + { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
5594 + { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
5595 + { }
5596 +};
5597 +
5598 +MODULE_DEVICE_TABLE(mdio, atheros_tbl);
Staging tree of Piotr Dymacz