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1 From 3cf9e2daca330a0ba89d3793ceb09037c788db46 Mon Sep 17 00:00:00 2001
2 From: Weijie Gao <weijie.gao@mediatek.com>
3 Date: Fri, 20 May 2022 11:22:49 +0800
4 Subject: [PATCH 10/25] pinctrl: mtmips: add support for MediaTek MT7621 SoC
5
6 This patch adds pinctrl support for MediaTek MT7621 SoC.
7 The MT7621 SoC supports pinconf, but it is not the same as mt7628.
8
9 Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
10 Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
11 ---
12 drivers/pinctrl/mtmips/Kconfig | 9 +
13 drivers/pinctrl/mtmips/Makefile | 1 +
14 drivers/pinctrl/mtmips/pinctrl-mt7621.c | 306 ++++++++++++++++++
15 .../pinctrl/mtmips/pinctrl-mtmips-common.c | 4 +-
16 .../pinctrl/mtmips/pinctrl-mtmips-common.h | 12 +
17 5 files changed, 330 insertions(+), 2 deletions(-)
18 create mode 100644 drivers/pinctrl/mtmips/pinctrl-mt7621.c
19
20 diff --git a/drivers/pinctrl/mtmips/Kconfig b/drivers/pinctrl/mtmips/Kconfig
21 index 844d5b743f..456f3ea25d 100644
22 --- a/drivers/pinctrl/mtmips/Kconfig
23 +++ b/drivers/pinctrl/mtmips/Kconfig
24 @@ -12,6 +12,15 @@ config PINCTRL_MT7620
25 The driver is controlled by a device tree node which contains
26 the pin mux functions for each available pin groups.
27
28 +config PINCTRL_MT7621
29 + bool "MediaTek MT7621 pin control driver"
30 + select PINCTRL_MTMIPS
31 + depends on SOC_MT7621 && PINCTRL_GENERIC
32 + help
33 + Support pin multiplexing control on MediaTek MT7621.
34 + The driver is controlled by a device tree node which contains
35 + the pin mux functions for each available pin groups.
36 +
37 config PINCTRL_MT7628
38 bool "MediaTek MT7628 pin control driver"
39 select PINCTRL_MTMIPS
40 diff --git a/drivers/pinctrl/mtmips/Makefile b/drivers/pinctrl/mtmips/Makefile
41 index ba945a89a7..8fece4f5fa 100644
42 --- a/drivers/pinctrl/mtmips/Makefile
43 +++ b/drivers/pinctrl/mtmips/Makefile
44 @@ -5,4 +5,5 @@ obj-$(CONFIG_PINCTRL_MTMIPS) += pinctrl-mtmips-common.o
45
46 # SoC Drivers
47 obj-$(CONFIG_PINCTRL_MT7620) += pinctrl-mt7620.o
48 +obj-$(CONFIG_PINCTRL_MT7621) += pinctrl-mt7621.o
49 obj-$(CONFIG_PINCTRL_MT7628) += pinctrl-mt7628.o
50 diff --git a/drivers/pinctrl/mtmips/pinctrl-mt7621.c b/drivers/pinctrl/mtmips/pinctrl-mt7621.c
51 new file mode 100644
52 index 0000000000..3e98a01bad
53 --- /dev/null
54 +++ b/drivers/pinctrl/mtmips/pinctrl-mt7621.c
55 @@ -0,0 +1,306 @@
56 +// SPDX-License-Identifier: GPL-2.0
57 +/*
58 + * Copyright (C) 2022 MediaTek Inc. All rights reserved.
59 + *
60 + * Author: Weijie Gao <weijie.gao@mediatek.com>
61 + */
62 +
63 +#include <dm.h>
64 +#include <dm/pinctrl.h>
65 +#include <dm/device_compat.h>
66 +#include <linux/bitops.h>
67 +#include <linux/io.h>
68 +
69 +#include "pinctrl-mtmips-common.h"
70 +
71 +#define SYSC_MAP_SIZE 0x100
72 +
73 +#define PAD_UART1_GPIO0_OFS 0x00
74 +#define PAD_UART3_I2C_OFS 0x04
75 +#define PAD_UART2_JTAG_OFS 0x08
76 +#define PAD_PERST_WDT_OFS 0x0c
77 +#define PAD_RGMII2_MDIO_OFS 0x10
78 +#define PAD_SDXC_SPI_OFS 0x14
79 +#define GPIOMODE_OFS 0x18
80 +#define PAD_BOPT_ESWINT_OFS 0x28
81 +
82 +#define ESWINT_SHIFT 20
83 +#define SDXC_SHIFT 18
84 +#define SPI_SHIFT 16
85 +#define RGMII2_SHIFT 15
86 +#define RGMII1_SHIFT 14
87 +#define MDIO_SHIFT 12
88 +#define PERST_SHIFT 10
89 +#define WDT_SHIFT 8
90 +#define JTAG_SHIFT 7
91 +#define UART2_SHIFT 5
92 +#define UART3_SHIFT 3
93 +#define I2C_SHIFT 2
94 +#define UART1_SHIFT 1
95 +#define GPIO0_SHIFT 0 /* Dummy */
96 +
97 +#define GM4_MASK 3
98 +
99 +#define E4_E2_M 0x03
100 +#define E4_E2_S 4
101 +#define PULL_UP BIT(3)
102 +#define PULL_DOWN BIT(2)
103 +#define SMT BIT(1)
104 +#define SR BIT(0)
105 +
106 +struct mt7621_pinctrl_priv {
107 + struct mtmips_pinctrl_priv mp;
108 +};
109 +
110 +#if CONFIG_IS_ENABLED(PINMUX)
111 +static const struct mtmips_pmx_func esw_int_grp[] = {
112 + FUNC("gpio", 1),
113 + FUNC("esw int", 0),
114 +};
115 +
116 +static const struct mtmips_pmx_func sdxc_grp[] = {
117 + FUNC("nand", 2),
118 + FUNC("gpio", 1),
119 + FUNC("sdxc", 0),
120 +};
121 +
122 +static const struct mtmips_pmx_func spi_grp[] = {
123 + FUNC("nand", 2),
124 + FUNC("gpio", 1),
125 + FUNC("spi", 0),
126 +};
127 +
128 +static const struct mtmips_pmx_func rgmii2_grp[] = {
129 + FUNC("gpio", 1),
130 + FUNC("rgmii", 0),
131 +};
132 +
133 +static const struct mtmips_pmx_func rgmii1_grp[] = {
134 + FUNC("gpio", 1),
135 + FUNC("rgmii", 0),
136 +};
137 +
138 +static const struct mtmips_pmx_func mdio_grp[] = {
139 + FUNC("gpio", 1),
140 + FUNC("mdio", 0),
141 +};
142 +
143 +static const struct mtmips_pmx_func perst_grp[] = {
144 + FUNC("refclk", 2),
145 + FUNC("gpio", 1),
146 + FUNC("pcie reset", 0),
147 +};
148 +
149 +static const struct mtmips_pmx_func wdt_grp[] = {
150 + FUNC("refclk", 2),
151 + FUNC("gpio", 1),
152 + FUNC("wdt rst", 0),
153 +};
154 +
155 +static const struct mtmips_pmx_func jtag_grp[] = {
156 + FUNC("gpio", 1),
157 + FUNC("jtag", 0),
158 +};
159 +
160 +static const struct mtmips_pmx_func uart2_grp[] = {
161 + FUNC("spdif", 3),
162 + FUNC("pcm", 2),
163 + FUNC("gpio", 1),
164 + FUNC("uart", 0),
165 +};
166 +
167 +static const struct mtmips_pmx_func uart3_grp[] = {
168 + FUNC("spdif", 3),
169 + FUNC("i2s", 2),
170 + FUNC("gpio", 1),
171 + FUNC("uart", 0),
172 +};
173 +
174 +static const struct mtmips_pmx_func i2c_grp[] = {
175 + FUNC("gpio", 1),
176 + FUNC("i2c", 0),
177 +};
178 +
179 +static const struct mtmips_pmx_func uart1_grp[] = {
180 + FUNC("gpio", 1),
181 + FUNC("uart", 0),
182 +};
183 +
184 +static const struct mtmips_pmx_func gpio0_grp[] = {
185 + FUNC("gpio", 0),
186 +};
187 +
188 +static const struct mtmips_pmx_group mt7621_pmx_data[] = {
189 + GRP_PCONF("esw int", esw_int_grp, GPIOMODE_OFS, ESWINT_SHIFT, 1,
190 + PAD_BOPT_ESWINT_OFS, 0),
191 + GRP_PCONF("sdxc", sdxc_grp, GPIOMODE_OFS, SDXC_SHIFT, GM4_MASK,
192 + PAD_SDXC_SPI_OFS, 16),
193 + GRP_PCONF("spi", spi_grp, GPIOMODE_OFS, SPI_SHIFT, GM4_MASK,
194 + PAD_SDXC_SPI_OFS, 0),
195 + GRP_PCONF("rgmii2", rgmii2_grp, GPIOMODE_OFS, RGMII2_SHIFT, 1,
196 + PAD_RGMII2_MDIO_OFS, 16),
197 + GRP("rgmii1", rgmii1_grp, GPIOMODE_OFS, RGMII1_SHIFT, 1),
198 + GRP_PCONF("mdio", mdio_grp, GPIOMODE_OFS, MDIO_SHIFT, GM4_MASK,
199 + PAD_RGMII2_MDIO_OFS, 0),
200 + GRP_PCONF("pcie reset", perst_grp, GPIOMODE_OFS, PERST_SHIFT, GM4_MASK,
201 + PAD_PERST_WDT_OFS, 16),
202 + GRP_PCONF("wdt", wdt_grp, GPIOMODE_OFS, WDT_SHIFT, GM4_MASK,
203 + PAD_PERST_WDT_OFS, 0),
204 + GRP_PCONF("jtag", jtag_grp, GPIOMODE_OFS, JTAG_SHIFT, 1,
205 + PAD_UART2_JTAG_OFS, 16),
206 + GRP_PCONF("uart2", uart2_grp, GPIOMODE_OFS, UART2_SHIFT, GM4_MASK,
207 + PAD_UART2_JTAG_OFS, 0),
208 + GRP_PCONF("uart3", uart3_grp, GPIOMODE_OFS, UART3_SHIFT, GM4_MASK,
209 + PAD_UART3_I2C_OFS, 16),
210 + GRP_PCONF("i2c", i2c_grp, GPIOMODE_OFS, I2C_SHIFT, 1,
211 + PAD_UART3_I2C_OFS, 0),
212 + GRP_PCONF("uart1", uart1_grp, GPIOMODE_OFS, UART1_SHIFT, 1,
213 + PAD_UART1_GPIO0_OFS, 16),
214 + GRP_PCONF("gpio0", gpio0_grp, GPIOMODE_OFS, GPIO0_SHIFT, 1,
215 + PAD_UART1_GPIO0_OFS, 0),
216 +};
217 +
218 +static int mt7621_get_groups_count(struct udevice *dev)
219 +{
220 + return ARRAY_SIZE(mt7621_pmx_data);
221 +}
222 +
223 +static const char *mt7621_get_group_name(struct udevice *dev,
224 + unsigned int selector)
225 +{
226 + return mt7621_pmx_data[selector].name;
227 +}
228 +#endif /* CONFIG_IS_ENABLED(PINMUX) */
229 +
230 +#if CONFIG_IS_ENABLED(PINCONF)
231 +static const struct pinconf_param mt7621_conf_params[] = {
232 + { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
233 + { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
234 + { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 },
235 + { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
236 + { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
237 + { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
238 + { "slew-rate", PIN_CONFIG_SLEW_RATE, 0 },
239 +};
240 +
241 +static const u32 mt7621_pconf_drv_strength_tbl[] = {2, 4, 6, 8};
242 +
243 +static int mt7621_pinconf_group_set(struct udevice *dev,
244 + unsigned int group_selector,
245 + unsigned int param, unsigned int arg)
246 +{
247 + struct mt7621_pinctrl_priv *priv = dev_get_priv(dev);
248 + const struct mtmips_pmx_group *grp = &mt7621_pmx_data[group_selector];
249 + u32 clr = 0, set = 0;
250 + int i;
251 +
252 + if (!grp->pconf_avail)
253 + return 0;
254 +
255 + switch (param) {
256 + case PIN_CONFIG_BIAS_DISABLE:
257 + clr = PULL_UP | PULL_DOWN;
258 + break;
259 +
260 + case PIN_CONFIG_BIAS_PULL_UP:
261 + clr = PULL_DOWN;
262 + set = PULL_UP;
263 + break;
264 +
265 + case PIN_CONFIG_BIAS_PULL_DOWN:
266 + clr = PULL_UP;
267 + set = PULL_DOWN;
268 + break;
269 +
270 + case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
271 + if (arg)
272 + set = SMT;
273 + else
274 + clr = SMT;
275 + break;
276 +
277 + case PIN_CONFIG_DRIVE_STRENGTH:
278 + for (i = 0; i < ARRAY_SIZE(mt7621_pconf_drv_strength_tbl); i++)
279 + if (mt7621_pconf_drv_strength_tbl[i] == arg)
280 + break;
281 +
282 + if (i >= ARRAY_SIZE(mt7621_pconf_drv_strength_tbl))
283 + return -EINVAL;
284 +
285 + clr = E4_E2_M << E4_E2_S;
286 + set = i << E4_E2_S;
287 + break;
288 +
289 + case PIN_CONFIG_SLEW_RATE:
290 + if (arg)
291 + set = SR;
292 + else
293 + clr = SR;
294 + break;
295 +
296 + default:
297 + return -EINVAL;
298 + }
299 +
300 + mtmips_pinctrl_reg_set(&priv->mp, grp->pconf_reg, grp->pconf_shift,
301 + clr, set);
302 +
303 + return 0;
304 +}
305 +#endif
306 +
307 +static int mt7621_pinctrl_probe(struct udevice *dev)
308 +{
309 + struct mt7621_pinctrl_priv *priv = dev_get_priv(dev);
310 + int ret = 0;
311 +
312 +#if CONFIG_IS_ENABLED(PINMUX)
313 + ret = mtmips_pinctrl_probe(&priv->mp, ARRAY_SIZE(mt7621_pmx_data),
314 + mt7621_pmx_data);
315 +#endif /* CONFIG_IS_ENABLED(PINMUX) */
316 +
317 + return ret;
318 +}
319 +
320 +static int mt7621_pinctrl_of_to_plat(struct udevice *dev)
321 +{
322 + struct mt7621_pinctrl_priv *priv = dev_get_priv(dev);
323 +
324 + priv->mp.base = (void __iomem *)dev_remap_addr_index(dev, 0);
325 +
326 + if (!priv->mp.base)
327 + return -EINVAL;
328 +
329 + return 0;
330 +}
331 +
332 +static const struct pinctrl_ops mt7621_pinctrl_ops = {
333 +#if CONFIG_IS_ENABLED(PINMUX)
334 + .get_groups_count = mt7621_get_groups_count,
335 + .get_group_name = mt7621_get_group_name,
336 + .get_functions_count = mtmips_get_functions_count,
337 + .get_function_name = mtmips_get_function_name,
338 + .pinmux_group_set = mtmips_pinmux_group_set,
339 +#endif /* CONFIG_IS_ENABLED(PINMUX) */
340 +#if CONFIG_IS_ENABLED(PINCONF)
341 + .pinconf_num_params = ARRAY_SIZE(mt7621_conf_params),
342 + .pinconf_params = mt7621_conf_params,
343 + .pinconf_group_set = mt7621_pinconf_group_set,
344 +#endif /* CONFIG_IS_ENABLED(PINCONF) */
345 + .set_state = pinctrl_generic_set_state,
346 +};
347 +
348 +static const struct udevice_id mt7621_pinctrl_ids[] = {
349 + { .compatible = "mediatek,mt7621-pinctrl" },
350 + { }
351 +};
352 +
353 +U_BOOT_DRIVER(mt7621_pinctrl) = {
354 + .name = "mt7621-pinctrl",
355 + .id = UCLASS_PINCTRL,
356 + .of_match = mt7621_pinctrl_ids,
357 + .of_to_plat = mt7621_pinctrl_of_to_plat,
358 + .ops = &mt7621_pinctrl_ops,
359 + .probe = mt7621_pinctrl_probe,
360 + .priv_auto = sizeof(struct mt7621_pinctrl_priv),
361 +};
362 diff --git a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c
363 index e361916eb2..869b781068 100644
364 --- a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c
365 +++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.c
366 @@ -13,8 +13,8 @@
367
368 #include "pinctrl-mtmips-common.h"
369
370 -static void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv,
371 - u32 reg, u32 shift, u32 mask, u32 value)
372 +void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv,
373 + u32 reg, u32 shift, u32 mask, u32 value)
374 {
375 u32 val;
376
377 diff --git a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h
378 index b51d8f009c..1f1023ef42 100644
379 --- a/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h
380 +++ b/drivers/pinctrl/mtmips/pinctrl-mtmips-common.h
381 @@ -22,6 +22,10 @@ struct mtmips_pmx_group {
382 u32 shift;
383 char mask;
384
385 + int pconf_avail;
386 + u32 pconf_reg;
387 + u32 pconf_shift;
388 +
389 int nfuncs;
390 const struct mtmips_pmx_func *funcs;
391 };
392 @@ -42,6 +46,14 @@ struct mtmips_pinctrl_priv {
393 { .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \
394 .funcs = (_funcs), .nfuncs = ARRAY_SIZE(_funcs) }
395
396 +#define GRP_PCONF(_name, _funcs, _reg, _shift, _mask, _pconf_reg, _pconf_shift) \
397 + { .name = (_name), .reg = (_reg), .shift = (_shift), .mask = (_mask), \
398 + .funcs = (_funcs), .nfuncs = ARRAY_SIZE(_funcs), .pconf_avail = 1, \
399 + .pconf_reg = (_pconf_reg), .pconf_shift = (_pconf_shift) }
400 +
401 +void mtmips_pinctrl_reg_set(struct mtmips_pinctrl_priv *priv,
402 + u32 reg, u32 shift, u32 mask, u32 value);
403 +
404 int mtmips_get_functions_count(struct udevice *dev);
405 const char *mtmips_get_function_name(struct udevice *dev,
406 unsigned int selector);
407 --
408 2.36.1
409
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