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1 From 777b8afb8179155353ec14b1d8153122410aba29 Mon Sep 17 00:00:00 2001
2 From: Vladimir Oltean <vladimir.oltean@nxp.com>
3 Date: Sat, 15 Jun 2024 20:00:27 +0800
4 Subject: [PATCH] net: phy: introduce core support for phy-mode = "10g-qxgmii"
5
6 10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport
7 specification. It uses the same signaling as USXGMII, but it multiplexes
8 4 ports over the link, resulting in a maximum speed of 2.5G per port.
9
10 Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean
11 either the single-port USXGMII or the quad-port 10G-QXGMII variant, and
12 they could get away just fine with that thus far. But there is a need to
13 distinguish between the 2 as far as SerDes drivers are concerned.
14
15 Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
16 Signed-off-by: Luo Jie <quic_luoj@quicinc.com>
17 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
18 Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
19 Signed-off-by: Paolo Abeni <pabeni@redhat.com>
20 ---
21 Documentation/networking/phy.rst | 6 ++++++
22 drivers/net/phy/phy-core.c | 1 +
23 drivers/net/phy/phylink.c | 9 ++++++++-
24 include/linux/phy.h | 4 ++++
25 include/linux/phylink.h | 1 +
26 5 files changed, 20 insertions(+), 1 deletion(-)
27
28 diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst
29 index 1283240d7620..f64641417c54 100644
30 --- a/Documentation/networking/phy.rst
31 +++ b/Documentation/networking/phy.rst
32 @@ -327,6 +327,12 @@ Some of the interface modes are described below:
33 This is the Penta SGMII mode, it is similar to QSGMII but it combines 5
34 SGMII lines into a single link compared to 4 on QSGMII.
35
36 +``PHY_INTERFACE_MODE_10G_QXGMII``
37 + Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII
38 + Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz
39 + SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved
40 + through symbol replication. The PCS expects the standard USXGMII code word.
41 +
42 Pause frames / flow control
43 ===========================
44
45 diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c
46 index 15f349e5995a..a235ea2264a7 100644
47 --- a/drivers/net/phy/phy-core.c
48 +++ b/drivers/net/phy/phy-core.c
49 @@ -141,6 +141,7 @@ int phy_interface_num_ports(phy_interface_t interface)
50 return 1;
51 case PHY_INTERFACE_MODE_QSGMII:
52 case PHY_INTERFACE_MODE_QUSGMII:
53 + case PHY_INTERFACE_MODE_10G_QXGMII:
54 return 4;
55 case PHY_INTERFACE_MODE_PSGMII:
56 return 5;
57 diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c
58 index 02427378acfd..6c24c48dcf0f 100644
59 --- a/drivers/net/phy/phylink.c
60 +++ b/drivers/net/phy/phylink.c
61 @@ -231,6 +231,7 @@ static int phylink_interface_max_speed(phy_interface_t interface)
62 return SPEED_1000;
63
64 case PHY_INTERFACE_MODE_2500BASEX:
65 + case PHY_INTERFACE_MODE_10G_QXGMII:
66 return SPEED_2500;
67
68 case PHY_INTERFACE_MODE_5GBASER:
69 @@ -500,7 +501,11 @@ static unsigned long phylink_get_capabilities(phy_interface_t interface,
70
71 switch (interface) {
72 case PHY_INTERFACE_MODE_USXGMII:
73 - caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD;
74 + caps |= MAC_10000FD | MAC_5000FD;
75 + fallthrough;
76 +
77 + case PHY_INTERFACE_MODE_10G_QXGMII:
78 + caps |= MAC_2500FD;
79 fallthrough;
80
81 case PHY_INTERFACE_MODE_RGMII_TXID:
82 @@ -926,6 +931,7 @@ static int phylink_parse_mode(struct phylink *pl,
83 case PHY_INTERFACE_MODE_5GBASER:
84 case PHY_INTERFACE_MODE_25GBASER:
85 case PHY_INTERFACE_MODE_USXGMII:
86 + case PHY_INTERFACE_MODE_10G_QXGMII:
87 case PHY_INTERFACE_MODE_10GKR:
88 case PHY_INTERFACE_MODE_10GBASER:
89 case PHY_INTERFACE_MODE_XLGMII:
90 diff --git a/include/linux/phy.h b/include/linux/phy.h
91 index e6e83304558e..205fccfc0f60 100644
92 --- a/include/linux/phy.h
93 +++ b/include/linux/phy.h
94 @@ -128,6 +128,7 @@ extern const int phy_10gbit_features_array[1];
95 * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN
96 * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII
97 * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN
98 + * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII
99 * @PHY_INTERFACE_MODE_MAX: Book keeping
100 *
101 * Describes the interface between the MAC and PHY.
102 @@ -168,6 +169,7 @@ typedef enum {
103 PHY_INTERFACE_MODE_10GKR,
104 PHY_INTERFACE_MODE_QUSGMII,
105 PHY_INTERFACE_MODE_1000BASEKX,
106 + PHY_INTERFACE_MODE_10G_QXGMII,
107 PHY_INTERFACE_MODE_MAX,
108 } phy_interface_t;
109
110 @@ -289,6 +291,8 @@ static inline const char *phy_modes(phy_interface_t interface)
111 return "100base-x";
112 case PHY_INTERFACE_MODE_QUSGMII:
113 return "qusgmii";
114 + case PHY_INTERFACE_MODE_10G_QXGMII:
115 + return "10g-qxgmii";
116 default:
117 return "unknown";
118 }
119 diff --git a/include/linux/phylink.h b/include/linux/phylink.h
120 index a30a692acc32..2381e07429a2 100644
121 --- a/include/linux/phylink.h
122 +++ b/include/linux/phylink.h
123 @@ -124,6 +130,7 @@ static unsigned int phylink_pcs_neg_mode(unsigned int mode,
124 case PHY_INTERFACE_MODE_QSGMII:
125 case PHY_INTERFACE_MODE_QUSGMII:
126 case PHY_INTERFACE_MODE_USXGMII:
127 + case PHY_INTERFACE_MODE_10G_QXGMII:
128 /* These protocols are designed for use with a PHY which
129 * communicates its negotiation result back to the MAC via
130 * inband communication. Note: there exist PHYs that run
131 @@ -654,6 +654,7 @@ static inline int phylink_get_link_timer_ns(phy_interface_t interface)
132 case PHY_INTERFACE_MODE_SGMII:
133 case PHY_INTERFACE_MODE_QSGMII:
134 case PHY_INTERFACE_MODE_USXGMII:
135 + case PHY_INTERFACE_MODE_10G_QXGMII:
136 return 1600000;
137
138 case PHY_INTERFACE_MODE_1000BASEX:
139 --
140 2.45.2
141
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