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1 From: Md Sadre Alam <quic_mdalam@quicinc.com>
2 Date: Sun, 22 Sep 2024 17:03:49 +0530
3 Subject: [PATCH] spi: spi-qpic: add driver for QCOM SPI NAND flash Interface
4
5 This driver implements support for the SPI-NAND mode of QCOM NAND Flash
6 Interface as a SPI-MEM controller with pipelined ECC capability.
7
8 Co-developed-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
9 Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
10 Co-developed-by: Varadarajan Narayanan <quic_varada@quicinc.com>
11 Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
12 Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
13 ---
14 --- a/drivers/mtd/nand/Makefile
15 +++ b/drivers/mtd/nand/Makefile
16 @@ -4,7 +4,11 @@ nandcore-objs := core.o bbt.o
17 obj-$(CONFIG_MTD_NAND_CORE) += nandcore.o
18 obj-$(CONFIG_MTD_NAND_ECC_MEDIATEK) += ecc-mtk.o
19 obj-$(CONFIG_MTD_NAND_MTK_BMT) += mtk_bmt.o mtk_bmt_v2.o mtk_bmt_bbt.o mtk_bmt_nmbm.o
20 +ifeq ($(CONFIG_SPI_QPIC_SNAND),y)
21 +obj-$(CONFIG_SPI_QPIC_SNAND) += qpic_common.o
22 +else
23 obj-$(CONFIG_MTD_NAND_QCOM) += qpic_common.o
24 +endif
25 obj-y += onenand/
26 obj-y += raw/
27 obj-y += spi/
28 --- a/drivers/spi/Kconfig
29 +++ b/drivers/spi/Kconfig
30 @@ -870,6 +870,14 @@ config SPI_QCOM_QSPI
31 help
32 QSPI(Quad SPI) driver for Qualcomm QSPI controller.
33
34 +config SPI_QPIC_SNAND
35 + bool "QPIC SNAND controller"
36 + depends on ARCH_QCOM || COMPILE_TEST
37 + help
38 + QPIC_SNAND (QPIC SPI NAND) driver for Qualcomm QPIC controller.
39 + QPIC controller supports both parallel nand and serial nand.
40 + This config will enable serial nand driver for QPIC controller.
41 +
42 config SPI_QUP
43 tristate "Qualcomm SPI controller with QUP interface"
44 depends on ARCH_QCOM || COMPILE_TEST
45 --- a/drivers/spi/Makefile
46 +++ b/drivers/spi/Makefile
47 @@ -110,6 +110,7 @@ obj-$(CONFIG_SPI_PXA2XX) += spi-pxa2xx-
48 obj-$(CONFIG_SPI_PXA2XX_PCI) += spi-pxa2xx-pci.o
49 obj-$(CONFIG_SPI_QCOM_GENI) += spi-geni-qcom.o
50 obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom-qspi.o
51 +obj-$(CONFIG_SPI_QPIC_SNAND) += spi-qpic-snand.o
52 obj-$(CONFIG_SPI_QUP) += spi-qup.o
53 obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
54 obj-$(CONFIG_SPI_ROCKCHIP_SFC) += spi-rockchip-sfc.o
55 --- /dev/null
56 +++ b/drivers/spi/spi-qpic-snand.c
57 @@ -0,0 +1,1634 @@
58 +/*
59 + * SPDX-License-Identifier: GPL-2.0
60 + *
61 + * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
62 + *
63 + * Authors:
64 + * Md Sadre Alam <quic_mdalam@quicinc.com>
65 + * Sricharan R <quic_srichara@quicinc.com>
66 + * Varadarajan Narayanan <quic_varada@quicinc.com>
67 + */
68 +#include <linux/bitops.h>
69 +#include <linux/clk.h>
70 +#include <linux/delay.h>
71 +#include <linux/dmaengine.h>
72 +#include <linux/dma-mapping.h>
73 +#include <linux/dma/qcom_adm.h>
74 +#include <linux/dma/qcom_bam_dma.h>
75 +#include <linux/module.h>
76 +#include <linux/of.h>
77 +#include <linux/platform_device.h>
78 +#include <linux/slab.h>
79 +#include <linux/mtd/nand-qpic-common.h>
80 +#include <linux/mtd/spinand.h>
81 +#include <linux/bitfield.h>
82 +
83 +#define NAND_FLASH_SPI_CFG 0xc0
84 +#define NAND_NUM_ADDR_CYCLES 0xc4
85 +#define NAND_BUSY_CHECK_WAIT_CNT 0xc8
86 +#define NAND_FLASH_FEATURES 0xf64
87 +
88 +/* QSPI NAND config reg bits */
89 +#define LOAD_CLK_CNTR_INIT_EN BIT(28)
90 +#define CLK_CNTR_INIT_VAL_VEC 0x924
91 +#define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16)
92 +#define FEA_STATUS_DEV_ADDR 0xc0
93 +#define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8)
94 +#define SPI_CFG BIT(0)
95 +#define SPI_NUM_ADDR 0xDA4DB
96 +#define SPI_WAIT_CNT 0x10
97 +#define QPIC_QSPI_NUM_CS 1
98 +#define SPI_TRANSFER_MODE_x1 BIT(29)
99 +#define SPI_TRANSFER_MODE_x4 (3 << 29)
100 +#define SPI_WP BIT(28)
101 +#define SPI_HOLD BIT(27)
102 +#define QPIC_SET_FEATURE BIT(31)
103 +
104 +#define SPINAND_RESET 0xff
105 +#define SPINAND_READID 0x9f
106 +#define SPINAND_GET_FEATURE 0x0f
107 +#define SPINAND_SET_FEATURE 0x1f
108 +#define SPINAND_READ 0x13
109 +#define SPINAND_ERASE 0xd8
110 +#define SPINAND_WRITE_EN 0x06
111 +#define SPINAND_PROGRAM_EXECUTE 0x10
112 +#define SPINAND_PROGRAM_LOAD 0x84
113 +
114 +#define ACC_FEATURE 0xe
115 +#define BAD_BLOCK_MARKER_SIZE 0x2
116 +#define OOB_BUF_SIZE 128
117 +#define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng)
118 +struct qpic_snand_op {
119 + u32 cmd_reg;
120 + u32 addr1_reg;
121 + u32 addr2_reg;
122 +};
123 +
124 +struct snandc_read_status {
125 + __le32 snandc_flash;
126 + __le32 snandc_buffer;
127 + __le32 snandc_erased_cw;
128 +};
129 +
130 +/*
131 + * ECC state struct
132 + * @corrected: ECC corrected
133 + * @bitflips: Max bit flip
134 + * @failed: ECC failed
135 + */
136 +struct qcom_ecc_stats {
137 + u32 corrected;
138 + u32 bitflips;
139 + u32 failed;
140 +};
141 +
142 +struct qpic_ecc {
143 + struct device *dev;
144 + int ecc_bytes_hw;
145 + int spare_bytes;
146 + int bbm_size;
147 + int ecc_mode;
148 + int bytes;
149 + int steps;
150 + int step_size;
151 + int strength;
152 + int cw_size;
153 + int cw_data;
154 + u32 cfg0;
155 + u32 cfg1;
156 + u32 cfg0_raw;
157 + u32 cfg1_raw;
158 + u32 ecc_buf_cfg;
159 + u32 ecc_bch_cfg;
160 + u32 clrflashstatus;
161 + u32 clrreadstatus;
162 + bool bch_enabled;
163 +};
164 +
165 +struct qpic_spi_nand {
166 + struct qcom_nand_controller *snandc;
167 + struct spi_controller *ctlr;
168 + struct mtd_info *mtd;
169 + struct clk *iomacro_clk;
170 + struct qpic_ecc *ecc;
171 + struct qcom_ecc_stats ecc_stats;
172 + struct nand_ecc_engine ecc_eng;
173 + u8 *data_buf;
174 + u8 *oob_buf;
175 + u32 wlen;
176 + __le32 addr1;
177 + __le32 addr2;
178 + __le32 cmd;
179 + u32 num_cw;
180 + bool oob_rw;
181 + bool page_rw;
182 + bool raw_rw;
183 +};
184 +
185 +static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc,
186 + int reg, int cw_offset, int read_size,
187 + int is_last_read_loc)
188 +{
189 + __le32 locreg_val;
190 + u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
191 + ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)
192 + << READ_LOCATION_LAST));
193 +
194 + locreg_val = cpu_to_le32(val);
195 +
196 + if (reg == NAND_READ_LOCATION_0)
197 + snandc->regs->read_location0 = locreg_val;
198 + else if (reg == NAND_READ_LOCATION_1)
199 + snandc->regs->read_location1 = locreg_val;
200 + else if (reg == NAND_READ_LOCATION_2)
201 + snandc->regs->read_location1 = locreg_val;
202 + else if (reg == NAND_READ_LOCATION_3)
203 + snandc->regs->read_location3 = locreg_val;
204 +}
205 +
206 +static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc,
207 + int reg, int cw_offset, int read_size,
208 + int is_last_read_loc)
209 +{
210 + __le32 locreg_val;
211 + u32 val = (((cw_offset) << READ_LOCATION_OFFSET) |
212 + ((read_size) << READ_LOCATION_SIZE) | ((is_last_read_loc)
213 + << READ_LOCATION_LAST));
214 +
215 + locreg_val = cpu_to_le32(val);
216 +
217 + if (reg == NAND_READ_LOCATION_LAST_CW_0)
218 + snandc->regs->read_location_last0 = locreg_val;
219 + else if (reg == NAND_READ_LOCATION_LAST_CW_1)
220 + snandc->regs->read_location_last1 = locreg_val;
221 + else if (reg == NAND_READ_LOCATION_LAST_CW_2)
222 + snandc->regs->read_location_last2 = locreg_val;
223 + else if (reg == NAND_READ_LOCATION_LAST_CW_3)
224 + snandc->regs->read_location_last3 = locreg_val;
225 +}
226 +
227 +static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand)
228 +{
229 + struct nand_ecc_engine *eng = nand->ecc.engine;
230 + struct qpic_spi_nand *qspi = ecceng_to_qspi(eng);
231 +
232 + return qspi->snandc;
233 +}
234 +
235 +static int qcom_spi_init(struct qcom_nand_controller *snandc)
236 +{
237 + u32 snand_cfg_val = 0x0;
238 + int ret;
239 +
240 + snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) |
241 + FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) |
242 + FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) |
243 + FIELD_PREP(SPI_CFG, 0);
244 +
245 + snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
246 + snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR);
247 + snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT);
248 +
249 + qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
250 +
251 + snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN;
252 + snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val);
253 +
254 + qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0);
255 +
256 + qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0);
257 + qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1,
258 + NAND_BAM_NEXT_SGL);
259 +
260 + ret = qcom_submit_descs(snandc);
261 + if (ret) {
262 + dev_err(snandc->dev, "failure in submitting spi init descriptor\n");
263 + return ret;
264 + }
265 +
266 + return ret;
267 +}
268 +
269 +static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section,
270 + struct mtd_oob_region *oobregion)
271 +{
272 + struct nand_device *nand = mtd_to_nanddev(mtd);
273 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
274 + struct qpic_ecc *qecc = snandc->qspi->ecc;
275 +
276 + if (section > 1)
277 + return -ERANGE;
278 +
279 + oobregion->length = qecc->ecc_bytes_hw + qecc->spare_bytes;
280 + oobregion->offset = mtd->oobsize - oobregion->length;
281 +
282 + return 0;
283 +}
284 +
285 +static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section,
286 + struct mtd_oob_region *oobregion)
287 +{
288 + struct nand_device *nand = mtd_to_nanddev(mtd);
289 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
290 + struct qpic_ecc *qecc = snandc->qspi->ecc;
291 +
292 + if (section)
293 + return -ERANGE;
294 +
295 + oobregion->length = qecc->steps * 4;
296 + oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size;
297 +
298 + return 0;
299 +}
300 +
301 +static const struct mtd_ooblayout_ops qcom_spi_ooblayout = {
302 + .ecc = qcom_spi_ooblayout_ecc,
303 + .free = qcom_spi_ooblayout_free,
304 +};
305 +
306 +static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand)
307 +{
308 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
309 + struct nand_ecc_props *conf = &nand->ecc.ctx.conf;
310 + struct mtd_info *mtd = nanddev_to_mtd(nand);
311 + int cwperpage, bad_block_byte;
312 + struct qpic_ecc *ecc_cfg;
313 +
314 + cwperpage = mtd->writesize / NANDC_STEP_SIZE;
315 + snandc->qspi->num_cw = cwperpage;
316 +
317 + ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL);
318 + if (!ecc_cfg)
319 + return -ENOMEM;
320 + snandc->qspi->oob_buf = kzalloc(mtd->writesize + mtd->oobsize,
321 + GFP_KERNEL);
322 + if (!snandc->qspi->oob_buf)
323 + return -ENOMEM;
324 +
325 + memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize);
326 +
327 + nand->ecc.ctx.priv = ecc_cfg;
328 + snandc->qspi->mtd = mtd;
329 +
330 + ecc_cfg->ecc_bytes_hw = 7;
331 + ecc_cfg->spare_bytes = 4;
332 + ecc_cfg->bbm_size = 1;
333 + ecc_cfg->bch_enabled = true;
334 + ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size;
335 +
336 + ecc_cfg->steps = 4;
337 + ecc_cfg->strength = 4;
338 + ecc_cfg->step_size = 512;
339 + ecc_cfg->cw_data = 516;
340 + ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes;
341 + bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1;
342 +
343 + mtd_set_ooblayout(mtd, &qcom_spi_ooblayout);
344 +
345 + ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
346 + FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) |
347 + FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) |
348 + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
349 + FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) |
350 + FIELD_PREP(STATUS_BFR_READ, 0) |
351 + FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) |
352 + FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes);
353 +
354 + ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
355 + FIELD_PREP(CS_ACTIVE_BSY, 0) |
356 + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) |
357 + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) |
358 + FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
359 + FIELD_PREP(WIDE_FLASH, 0) |
360 + FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled);
361 +
362 + ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) |
363 + FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) |
364 + FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) |
365 + FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0);
366 +
367 + ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) |
368 + FIELD_PREP(CS_ACTIVE_BSY, 0) |
369 + FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) |
370 + FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) |
371 + FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) |
372 + FIELD_PREP(WIDE_FLASH, 0) |
373 + FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1);
374 +
375 + ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) |
376 + FIELD_PREP(ECC_SW_RESET, 0) |
377 + FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) |
378 + FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) |
379 + FIELD_PREP(ECC_MODE_MASK, 0) |
380 + FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw);
381 +
382 + ecc_cfg->ecc_buf_cfg = 0x203 << NUM_STEPS;
383 + ecc_cfg->clrflashstatus = FS_READY_BSY_N;
384 + ecc_cfg->clrreadstatus = 0xc0;
385 +
386 + conf->step_size = ecc_cfg->step_size;
387 + conf->strength = ecc_cfg->strength;
388 +
389 + snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET);
390 + snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET);
391 +
392 + dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n",
393 + ecc_cfg->strength, ecc_cfg->step_size);
394 +
395 + return 0;
396 +}
397 +
398 +static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand)
399 +{
400 + struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
401 +
402 + kfree(ecc_cfg);
403 +}
404 +
405 +static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand,
406 + struct nand_page_io_req *req)
407 +{
408 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
409 + struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand);
410 +
411 + snandc->qspi->ecc = ecc_cfg;
412 + snandc->qspi->raw_rw = false;
413 + snandc->qspi->oob_rw = false;
414 + snandc->qspi->page_rw = false;
415 +
416 + if (req->datalen)
417 + snandc->qspi->page_rw = true;
418 +
419 + if (req->ooblen)
420 + snandc->qspi->oob_rw = true;
421 +
422 + if (req->mode == MTD_OPS_RAW)
423 + snandc->qspi->raw_rw = true;
424 +
425 + return 0;
426 +}
427 +
428 +static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand,
429 + struct nand_page_io_req *req)
430 +{
431 + struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand);
432 + struct mtd_info *mtd = nanddev_to_mtd(nand);
433 +
434 + if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ)
435 + return 0;
436 +
437 + if (snandc->qspi->ecc_stats.failed)
438 + mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed;
439 + else
440 + mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected;
441 +
442 + if (snandc->qspi->ecc_stats.failed)
443 + return -EBADMSG;
444 + else
445 + return snandc->qspi->ecc_stats.bitflips;
446 +}
447 +
448 +static struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = {
449 + .init_ctx = qcom_spi_ecc_init_ctx_pipelined,
450 + .cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined,
451 + .prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined,
452 + .finish_io_req = qcom_spi_ecc_finish_io_req_pipelined,
453 +};
454 +
455 +/* helper to configure location register values */
456 +static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg,
457 + int cw_offset, int read_size, int is_last_read_loc)
458 +{
459 + int reg_base = NAND_READ_LOCATION_0;
460 + int num_cw = snandc->qspi->num_cw;
461 +
462 + if (cw == (num_cw - 1))
463 + reg_base = NAND_READ_LOCATION_LAST_CW_0;
464 +
465 + reg_base += reg * 4;
466 +
467 + if (cw == (num_cw - 1))
468 + return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset,
469 + read_size, is_last_read_loc);
470 + else
471 + return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset,
472 + read_size, is_last_read_loc);
473 +}
474 +
475 +static void
476 +qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw)
477 +{
478 + __le32 *reg = &snandc->regs->read_location0;
479 + int num_cw = snandc->qspi->num_cw;
480 +
481 + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL);
482 + if (cw == (num_cw - 1)) {
483 + reg = &snandc->regs->read_location_last0;
484 + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4,
485 + NAND_BAM_NEXT_SGL);
486 + }
487 +
488 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
489 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
490 +
491 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0);
492 + qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1,
493 + NAND_BAM_NEXT_SGL);
494 +}
495 +
496 +static int qcom_spi_block_erase(struct qcom_nand_controller *snandc)
497 +{
498 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
499 + int ret;
500 +
501 + snandc->buf_count = 0;
502 + snandc->buf_start = 0;
503 + qcom_clear_read_regs(snandc);
504 + qcom_clear_bam_transaction(snandc);
505 +
506 + snandc->regs->cmd = snandc->qspi->cmd;
507 + snandc->regs->addr0 = snandc->qspi->addr1;
508 + snandc->regs->addr1 = snandc->qspi->addr2;
509 + snandc->regs->cfg0 = cpu_to_le32(ecc_cfg->cfg0_raw & ~(7 << CW_PER_PAGE));
510 + snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw);
511 + snandc->regs->exec = cpu_to_le32(1);
512 +
513 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
514 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL);
515 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
516 +
517 + ret = qcom_submit_descs(snandc);
518 + if (ret) {
519 + dev_err(snandc->dev, "failure to erase block\n");
520 + return ret;
521 + }
522 +
523 + return 0;
524 +}
525 +
526 +static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc,
527 + bool use_ecc, int cw)
528 +{
529 + __le32 *reg = &snandc->regs->read_location0;
530 + int num_cw = snandc->qspi->num_cw;
531 +
532 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
533 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
534 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
535 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
536 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
537 + NAND_ERASED_CW_DETECT_CFG, 1,
538 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
539 +
540 + if (cw == (num_cw - 1)) {
541 + reg = &snandc->regs->read_location_last0;
542 + qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL);
543 + }
544 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
545 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
546 +
547 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0);
548 +}
549 +
550 +static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc,
551 + const struct spi_mem_op *op)
552 +{
553 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
554 + struct mtd_info *mtd = snandc->qspi->mtd;
555 + int size, ret = 0;
556 + int col, bbpos;
557 + u32 cfg0, cfg1, ecc_bch_cfg;
558 + u32 num_cw = snandc->qspi->num_cw;
559 +
560 + qcom_clear_bam_transaction(snandc);
561 + qcom_clear_read_regs(snandc);
562 +
563 + size = ecc_cfg->cw_size;
564 + col = ecc_cfg->cw_size * (num_cw - 1);
565 +
566 + memset(snandc->data_buffer, 0xff, size);
567 + snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
568 + snandc->regs->addr1 = snandc->qspi->addr2;
569 +
570 + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
571 + 0 << CW_PER_PAGE;
572 + cfg1 = ecc_cfg->cfg1_raw;
573 + ecc_bch_cfg = 1 << ECC_CFG_ECC_DISABLE;
574 +
575 + snandc->regs->cmd = snandc->qspi->cmd;
576 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
577 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
578 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
579 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
580 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
581 + snandc->regs->exec = cpu_to_le32(1);
582 +
583 + qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1);
584 +
585 + qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1);
586 +
587 + qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0);
588 +
589 + ret = qcom_submit_descs(snandc);
590 + if (ret) {
591 + dev_err(snandc->dev, "failed to read last cw\n");
592 + return ret;
593 + }
594 +
595 + qcom_nandc_dev_to_mem(snandc, true);
596 + u32 flash = le32_to_cpu(snandc->reg_read_buf[0]);
597 +
598 + if (flash & (FS_OP_ERR | FS_MPU_ERR))
599 + return -EIO;
600 +
601 + bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
602 +
603 + if (snandc->data_buffer[bbpos] == 0xff)
604 + snandc->data_buffer[bbpos + 1] = 0xff;
605 + if (snandc->data_buffer[bbpos] != 0xff)
606 + snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos];
607 +
608 + memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes);
609 +
610 + return ret;
611 +}
612 +
613 +static int qcom_spi_check_error(struct qcom_nand_controller *snandc, u8 *data_buf, u8 *oob_buf)
614 +{
615 + struct snandc_read_status *buf;
616 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
617 + int i, num_cw = snandc->qspi->num_cw;
618 + bool flash_op_err = false, erased;
619 + unsigned int max_bitflips = 0;
620 + unsigned int uncorrectable_cws = 0;
621 +
622 + snandc->qspi->ecc_stats.failed = 0;
623 + snandc->qspi->ecc_stats.corrected = 0;
624 +
625 + qcom_nandc_dev_to_mem(snandc, true);
626 + buf = (struct snandc_read_status *)snandc->reg_read_buf;
627 +
628 + for (i = 0; i < num_cw; i++, buf++) {
629 + u32 flash, buffer, erased_cw;
630 + int data_len, oob_len;
631 +
632 + if (i == (num_cw - 1)) {
633 + data_len = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
634 + oob_len = num_cw << 2;
635 + } else {
636 + data_len = ecc_cfg->cw_data;
637 + oob_len = 0;
638 + }
639 +
640 + flash = le32_to_cpu(buf->snandc_flash);
641 + buffer = le32_to_cpu(buf->snandc_buffer);
642 + erased_cw = le32_to_cpu(buf->snandc_erased_cw);
643 +
644 + if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) {
645 + if (ecc_cfg->bch_enabled)
646 + erased = (erased_cw & ERASED_CW) == ERASED_CW;
647 + else
648 + erased = false;
649 +
650 + if (!erased)
651 + uncorrectable_cws |= BIT(i);
652 +
653 + } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) {
654 + flash_op_err = true;
655 + } else {
656 + unsigned int stat;
657 +
658 + stat = buffer & BS_CORRECTABLE_ERR_MSK;
659 + snandc->qspi->ecc_stats.corrected += stat;
660 + max_bitflips = max(max_bitflips, stat);
661 + }
662 +
663 + if (data_buf)
664 + data_buf += data_len;
665 + if (oob_buf)
666 + oob_buf += oob_len + ecc_cfg->bytes;
667 + }
668 +
669 + if (flash_op_err)
670 + return -EIO;
671 +
672 + if (!uncorrectable_cws)
673 + snandc->qspi->ecc_stats.bitflips = max_bitflips;
674 + else
675 + snandc->qspi->ecc_stats.failed++;
676 +
677 + return 0;
678 +}
679 +
680 +static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt)
681 +{
682 + int i;
683 +
684 + qcom_nandc_dev_to_mem(snandc, true);
685 +
686 + for (i = 0; i < cw_cnt; i++) {
687 + u32 flash = le32_to_cpu(snandc->reg_read_buf[i]);
688 +
689 + if (flash & (FS_OP_ERR | FS_MPU_ERR))
690 + return -EIO;
691 + }
692 +
693 + return 0;
694 +}
695 +
696 +static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf,
697 + u8 *oob_buf, int cw)
698 +{
699 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
700 + struct mtd_info *mtd = snandc->qspi->mtd;
701 + int data_size1, data_size2, oob_size1, oob_size2;
702 + int ret, reg_off = FLASH_BUF_ACC, read_loc = 0;
703 + int raw_cw = cw;
704 + u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
705 + int col;
706 +
707 + snandc->buf_count = 0;
708 + snandc->buf_start = 0;
709 + qcom_clear_read_regs(snandc);
710 + qcom_clear_bam_transaction(snandc);
711 + raw_cw = num_cw - 1;
712 +
713 + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
714 + 0 << CW_PER_PAGE;
715 + cfg1 = ecc_cfg->cfg1_raw;
716 + ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
717 +
718 + col = ecc_cfg->cw_size * cw;
719 +
720 + snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
721 + snandc->regs->addr1 = snandc->qspi->addr2;
722 + snandc->regs->cmd = snandc->qspi->cmd;
723 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
724 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
725 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
726 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
727 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
728 + snandc->regs->exec = cpu_to_le32(1);
729 +
730 + qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1);
731 +
732 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
733 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
734 + qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0);
735 +
736 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
737 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
738 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
739 + NAND_ERASED_CW_DETECT_CFG, 1,
740 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
741 +
742 + data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
743 + oob_size1 = ecc_cfg->bbm_size;
744 +
745 + if (cw == (num_cw - 1)) {
746 + data_size2 = NANDC_STEP_SIZE - data_size1 -
747 + ((num_cw - 1) * 4);
748 + oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw +
749 + ecc_cfg->spare_bytes;
750 + } else {
751 + data_size2 = ecc_cfg->cw_data - data_size1;
752 + oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
753 + }
754 +
755 + qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0);
756 + read_loc += data_size1;
757 +
758 + qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0);
759 + read_loc += oob_size1;
760 +
761 + qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0);
762 + read_loc += data_size2;
763 +
764 + qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1);
765 +
766 + qcom_spi_config_cw_read(snandc, false, raw_cw);
767 +
768 + qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0);
769 + reg_off += data_size1;
770 +
771 + qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0);
772 + reg_off += oob_size1;
773 +
774 + qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0);
775 + reg_off += data_size2;
776 +
777 + qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0);
778 +
779 + ret = qcom_submit_descs(snandc);
780 + if (ret) {
781 + dev_err(snandc->dev, "failure to read raw cw %d\n", cw);
782 + return ret;
783 + }
784 +
785 + return qcom_spi_check_raw_flash_errors(snandc, 1);
786 +}
787 +
788 +static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc,
789 + const struct spi_mem_op *op)
790 +{
791 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
792 + u8 *data_buf = NULL, *oob_buf = NULL;
793 + int ret, cw;
794 + u32 num_cw = snandc->qspi->num_cw;
795 +
796 + if (snandc->qspi->page_rw)
797 + data_buf = op->data.buf.in;
798 +
799 + oob_buf = snandc->qspi->oob_buf;
800 + memset(oob_buf, 0xff, OOB_BUF_SIZE);
801 +
802 + for (cw = 0; cw < num_cw; cw++) {
803 + ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw);
804 + if (ret)
805 + return ret;
806 +
807 + if (data_buf)
808 + data_buf += ecc_cfg->cw_data;
809 + if (oob_buf)
810 + oob_buf += ecc_cfg->bytes;
811 + }
812 +
813 + return 0;
814 +}
815 +
816 +static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc,
817 + const struct spi_mem_op *op)
818 +{
819 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
820 + u8 *data_buf = NULL, *data_buf_start, *oob_buf = NULL, *oob_buf_start;
821 + int ret, i;
822 + u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
823 +
824 + data_buf = op->data.buf.in;
825 + data_buf_start = data_buf;
826 +
827 + oob_buf = snandc->qspi->oob_buf;
828 + oob_buf_start = oob_buf;
829 +
830 + snandc->buf_count = 0;
831 + snandc->buf_start = 0;
832 + qcom_clear_read_regs(snandc);
833 +
834 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
835 + (num_cw - 1) << CW_PER_PAGE;
836 + cfg1 = ecc_cfg->cfg1;
837 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
838 +
839 + snandc->regs->addr0 = snandc->qspi->addr1;
840 + snandc->regs->addr1 = snandc->qspi->addr2;
841 + snandc->regs->cmd = snandc->qspi->cmd;
842 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
843 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
844 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
845 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
846 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
847 + snandc->regs->exec = cpu_to_le32(1);
848 +
849 + qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
850 +
851 + qcom_clear_bam_transaction(snandc);
852 +
853 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
854 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
855 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
856 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
857 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
858 + NAND_ERASED_CW_DETECT_CFG, 1,
859 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
860 +
861 + for (i = 0; i < num_cw; i++) {
862 + int data_size, oob_size;
863 +
864 + if (i == (num_cw - 1)) {
865 + data_size = 512 - ((num_cw - 1) << 2);
866 + oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
867 + ecc_cfg->spare_bytes;
868 + } else {
869 + data_size = ecc_cfg->cw_data;
870 + oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
871 + }
872 +
873 + if (data_buf && oob_buf) {
874 + qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0);
875 + qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1);
876 + } else if (data_buf) {
877 + qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1);
878 + } else {
879 + qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
880 + }
881 +
882 + qcom_spi_config_cw_read(snandc, true, i);
883 +
884 + if (data_buf)
885 + qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf,
886 + data_size, 0);
887 + if (oob_buf) {
888 + int j;
889 +
890 + for (j = 0; j < ecc_cfg->bbm_size; j++)
891 + *oob_buf++ = 0xff;
892 +
893 + qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
894 + oob_buf, oob_size, 0);
895 + }
896 +
897 + if (data_buf)
898 + data_buf += data_size;
899 + if (oob_buf)
900 + oob_buf += oob_size;
901 + }
902 +
903 + ret = qcom_submit_descs(snandc);
904 + if (ret) {
905 + dev_err(snandc->dev, "failure to read page\n");
906 + return ret;
907 + }
908 +
909 + return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start);
910 +}
911 +
912 +static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc,
913 + const struct spi_mem_op *op)
914 +{
915 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
916 + u8 *data_buf = NULL, *data_buf_start, *oob_buf = NULL, *oob_buf_start;
917 + int ret, i;
918 + u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw;
919 +
920 + oob_buf = op->data.buf.in;
921 + oob_buf_start = oob_buf;
922 +
923 + data_buf_start = data_buf;
924 +
925 + snandc->buf_count = 0;
926 + snandc->buf_start = 0;
927 + qcom_clear_read_regs(snandc);
928 + qcom_clear_bam_transaction(snandc);
929 +
930 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
931 + (num_cw - 1) << CW_PER_PAGE;
932 + cfg1 = ecc_cfg->cfg1;
933 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
934 +
935 + snandc->regs->addr0 = snandc->qspi->addr1;
936 + snandc->regs->addr1 = snandc->qspi->addr2;
937 + snandc->regs->cmd = snandc->qspi->cmd;
938 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
939 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
940 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
941 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
942 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
943 + snandc->regs->exec = cpu_to_le32(1);
944 +
945 + qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1);
946 +
947 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
948 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
949 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr,
950 + NAND_ERASED_CW_DETECT_CFG, 1, 0);
951 + qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set,
952 + NAND_ERASED_CW_DETECT_CFG, 1,
953 + NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL);
954 +
955 + for (i = 0; i < num_cw; i++) {
956 + int data_size, oob_size;
957 +
958 + if (i == (num_cw - 1)) {
959 + data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
960 + oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
961 + ecc_cfg->spare_bytes;
962 + } else {
963 + data_size = ecc_cfg->cw_data;
964 + oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
965 + }
966 +
967 + qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1);
968 +
969 + qcom_spi_config_cw_read(snandc, true, i);
970 +
971 + if (oob_buf) {
972 + int j;
973 +
974 + for (j = 0; j < ecc_cfg->bbm_size; j++)
975 + *oob_buf++ = 0xff;
976 +
977 + qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size,
978 + oob_buf, oob_size, 0);
979 + }
980 +
981 + if (oob_buf)
982 + oob_buf += oob_size;
983 + }
984 +
985 + ret = qcom_submit_descs(snandc);
986 + if (ret) {
987 + dev_err(snandc->dev, "failure to read oob\n");
988 + return ret;
989 + }
990 +
991 + return qcom_spi_check_error(snandc, data_buf_start, oob_buf_start);
992 +}
993 +
994 +static int qcom_spi_read_page(struct qcom_nand_controller *snandc,
995 + const struct spi_mem_op *op)
996 +{
997 + if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
998 + return qcom_spi_read_page_raw(snandc, op);
999 +
1000 + if (snandc->qspi->page_rw)
1001 + return qcom_spi_read_page_ecc(snandc, op);
1002 +
1003 + if (snandc->qspi->oob_rw && snandc->qspi->raw_rw)
1004 + return qcom_spi_read_last_cw(snandc, op);
1005 +
1006 + if (snandc->qspi->oob_rw)
1007 + return qcom_spi_read_page_oob(snandc, op);
1008 +
1009 + return 0;
1010 +}
1011 +
1012 +static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc)
1013 +{
1014 + qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0);
1015 + qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0);
1016 + qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG,
1017 + 1, NAND_BAM_NEXT_SGL);
1018 +}
1019 +
1020 +static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc)
1021 +{
1022 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL);
1023 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1024 + qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL);
1025 +
1026 + qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0);
1027 + qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1,
1028 + NAND_BAM_NEXT_SGL);
1029 +}
1030 +
1031 +static int qcom_spi_program_raw(struct qcom_nand_controller *snandc,
1032 + const struct spi_mem_op *op)
1033 +{
1034 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1035 + struct mtd_info *mtd = snandc->qspi->mtd;
1036 + u8 *data_buf = NULL, *oob_buf = NULL;
1037 + int i, ret;
1038 + int num_cw = snandc->qspi->num_cw;
1039 + u32 cfg0, cfg1, ecc_bch_cfg;
1040 +
1041 + cfg0 = (ecc_cfg->cfg0_raw & ~(7U << CW_PER_PAGE)) |
1042 + (num_cw - 1) << CW_PER_PAGE;
1043 + cfg1 = ecc_cfg->cfg1_raw;
1044 + ecc_bch_cfg = ECC_CFG_ECC_DISABLE;
1045 +
1046 + data_buf = snandc->qspi->data_buf;
1047 +
1048 + oob_buf = snandc->qspi->oob_buf;
1049 + memset(oob_buf, 0xff, OOB_BUF_SIZE);
1050 +
1051 + snandc->buf_count = 0;
1052 + snandc->buf_start = 0;
1053 + qcom_clear_read_regs(snandc);
1054 + qcom_clear_bam_transaction(snandc);
1055 +
1056 + snandc->regs->addr0 = snandc->qspi->addr1;
1057 + snandc->regs->addr1 = snandc->qspi->addr2;
1058 + snandc->regs->cmd = snandc->qspi->cmd;
1059 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1060 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1061 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1062 + snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus);
1063 + snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus);
1064 + snandc->regs->exec = cpu_to_le32(1);
1065 +
1066 + qcom_spi_config_page_write(snandc);
1067 +
1068 + for (i = 0; i < num_cw; i++) {
1069 + int data_size1, data_size2, oob_size1, oob_size2;
1070 + int reg_off = FLASH_BUF_ACC;
1071 +
1072 + data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1);
1073 + oob_size1 = ecc_cfg->bbm_size;
1074 +
1075 + if ((i == (num_cw - 1))) {
1076 + data_size2 = NANDC_STEP_SIZE - data_size1 -
1077 + ((num_cw - 1) << 2);
1078 + oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1079 + ecc_cfg->spare_bytes;
1080 + } else {
1081 + data_size2 = ecc_cfg->cw_data - data_size1;
1082 + oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes;
1083 + }
1084 +
1085 + qcom_write_data_dma(snandc, reg_off, data_buf, data_size1,
1086 + NAND_BAM_NO_EOT);
1087 + reg_off += data_size1;
1088 + data_buf += data_size1;
1089 +
1090 + qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1,
1091 + NAND_BAM_NO_EOT);
1092 + oob_buf += oob_size1;
1093 + reg_off += oob_size1;
1094 +
1095 + qcom_write_data_dma(snandc, reg_off, data_buf, data_size2,
1096 + NAND_BAM_NO_EOT);
1097 + reg_off += data_size2;
1098 + data_buf += data_size2;
1099 +
1100 + qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0);
1101 + oob_buf += oob_size2;
1102 +
1103 + qcom_spi_config_cw_write(snandc);
1104 + }
1105 +
1106 + ret = qcom_submit_descs(snandc);
1107 + if (ret) {
1108 + dev_err(snandc->dev, "failure to write raw page\n");
1109 + return ret;
1110 + }
1111 +
1112 + return 0;
1113 +}
1114 +
1115 +static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc,
1116 + const struct spi_mem_op *op)
1117 +{
1118 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1119 + u8 *data_buf = NULL, *oob_buf = NULL;
1120 + int i, ret;
1121 + int num_cw = snandc->qspi->num_cw;
1122 + u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1123 +
1124 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
1125 + (num_cw - 1) << CW_PER_PAGE;
1126 + cfg1 = ecc_cfg->cfg1;
1127 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1128 + ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1129 +
1130 + if (snandc->qspi->data_buf)
1131 + data_buf = snandc->qspi->data_buf;
1132 +
1133 + oob_buf = snandc->qspi->oob_buf;
1134 +
1135 + snandc->buf_count = 0;
1136 + snandc->buf_start = 0;
1137 + qcom_clear_read_regs(snandc);
1138 + qcom_clear_bam_transaction(snandc);
1139 +
1140 + snandc->regs->addr0 = snandc->qspi->addr1;
1141 + snandc->regs->addr1 = snandc->qspi->addr2;
1142 + snandc->regs->cmd = snandc->qspi->cmd;
1143 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1144 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1145 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1146 + snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1147 + snandc->regs->exec = cpu_to_le32(1);
1148 +
1149 + qcom_spi_config_page_write(snandc);
1150 +
1151 + for (i = 0; i < num_cw; i++) {
1152 + int data_size, oob_size;
1153 +
1154 + if (i == (num_cw - 1)) {
1155 + data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1156 + oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw +
1157 + ecc_cfg->spare_bytes;
1158 + } else {
1159 + data_size = ecc_cfg->cw_data;
1160 + oob_size = ecc_cfg->bytes;
1161 + }
1162 +
1163 + if (data_buf)
1164 + qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size,
1165 + i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0);
1166 +
1167 + if (i == (num_cw - 1)) {
1168 + if (oob_buf) {
1169 + oob_buf += ecc_cfg->bbm_size;
1170 + qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size,
1171 + oob_buf, oob_size, 0);
1172 + }
1173 + }
1174 +
1175 + qcom_spi_config_cw_write(snandc);
1176 +
1177 + if (data_buf)
1178 + data_buf += data_size;
1179 + if (oob_buf)
1180 + oob_buf += oob_size;
1181 + }
1182 +
1183 + ret = qcom_submit_descs(snandc);
1184 + if (ret) {
1185 + dev_err(snandc->dev, "failure to write page\n");
1186 + return ret;
1187 + }
1188 +
1189 + return 0;
1190 +}
1191 +
1192 +static int qcom_spi_program_oob(struct qcom_nand_controller *snandc,
1193 + const struct spi_mem_op *op)
1194 +{
1195 + struct qpic_ecc *ecc_cfg = snandc->qspi->ecc;
1196 + u8 *oob_buf = NULL;
1197 + int ret, col, data_size, oob_size;
1198 + int num_cw = snandc->qspi->num_cw;
1199 + u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg;
1200 +
1201 + cfg0 = (ecc_cfg->cfg0 & ~(7U << CW_PER_PAGE)) |
1202 + (num_cw - 1) << CW_PER_PAGE;
1203 + cfg1 = ecc_cfg->cfg1;
1204 + ecc_bch_cfg = ecc_cfg->ecc_bch_cfg;
1205 + ecc_buf_cfg = ecc_cfg->ecc_buf_cfg;
1206 +
1207 + col = ecc_cfg->cw_size * (num_cw - 1);
1208 +
1209 + oob_buf = snandc->qspi->data_buf;
1210 +
1211 + snandc->buf_count = 0;
1212 + snandc->buf_start = 0;
1213 + qcom_clear_read_regs(snandc);
1214 + qcom_clear_bam_transaction(snandc);
1215 + snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col));
1216 + snandc->regs->addr1 = snandc->qspi->addr2;
1217 + snandc->regs->cmd = snandc->qspi->cmd;
1218 + snandc->regs->cfg0 = cpu_to_le32(cfg0);
1219 + snandc->regs->cfg1 = cpu_to_le32(cfg1);
1220 + snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg);
1221 + snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg);
1222 + snandc->regs->exec = cpu_to_le32(1);
1223 +
1224 + /* calculate the data and oob size for the last codeword/step */
1225 + data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2);
1226 + oob_size = snandc->qspi->mtd->oobavail;
1227 +
1228 + memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data);
1229 + /* override new oob content to last codeword */
1230 + mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size,
1231 + oob_buf, 0, snandc->qspi->mtd->oobavail);
1232 + qcom_spi_config_page_write(snandc);
1233 + qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0);
1234 + qcom_spi_config_cw_write(snandc);
1235 +
1236 + ret = qcom_submit_descs(snandc);
1237 + if (ret) {
1238 + dev_err(snandc->dev, "failure to write oob\n");
1239 + return ret;
1240 + }
1241 +
1242 + return 0;
1243 +}
1244 +
1245 +static int qcom_spi_program_execute(struct qcom_nand_controller *snandc,
1246 + const struct spi_mem_op *op)
1247 +{
1248 + if (snandc->qspi->page_rw && snandc->qspi->raw_rw)
1249 + return qcom_spi_program_raw(snandc, op);
1250 +
1251 + if (snandc->qspi->page_rw)
1252 + return qcom_spi_program_ecc(snandc, op);
1253 +
1254 + if (snandc->qspi->oob_rw)
1255 + return qcom_spi_program_oob(snandc, op);
1256 +
1257 + return 0;
1258 +}
1259 +
1260 +static u32 qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode)
1261 +{
1262 + u32 cmd = 0x0;
1263 +
1264 + switch (opcode) {
1265 + case SPINAND_RESET:
1266 + cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE);
1267 + break;
1268 + case SPINAND_READID:
1269 + cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID);
1270 + break;
1271 + case SPINAND_GET_FEATURE:
1272 + cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE);
1273 + break;
1274 + case SPINAND_SET_FEATURE:
1275 + cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE |
1276 + QPIC_SET_FEATURE);
1277 + break;
1278 + case SPINAND_READ:
1279 + if (snandc->qspi->raw_rw) {
1280 + cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1281 + SPI_WP | SPI_HOLD | OP_PAGE_READ);
1282 + } else {
1283 + cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1284 + SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC);
1285 + }
1286 +
1287 + break;
1288 + case SPINAND_ERASE:
1289 + cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP |
1290 + SPI_HOLD | SPI_TRANSFER_MODE_x1;
1291 + break;
1292 + case SPINAND_WRITE_EN:
1293 + cmd = SPINAND_WRITE_EN;
1294 + break;
1295 + case SPINAND_PROGRAM_EXECUTE:
1296 + cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 |
1297 + SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE);
1298 + break;
1299 + case SPINAND_PROGRAM_LOAD:
1300 + cmd = SPINAND_PROGRAM_LOAD;
1301 + break;
1302 + default:
1303 + dev_err(snandc->dev, "Opcode not supported: %u\n", opcode);
1304 + return -EOPNOTSUPP;
1305 + }
1306 +
1307 + return cmd;
1308 +}
1309 +
1310 +static int qcom_spi_write_page(struct qcom_nand_controller *snandc,
1311 + const struct spi_mem_op *op)
1312 +{
1313 + struct qpic_snand_op s_op = {};
1314 + u32 cmd;
1315 +
1316 + cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
1317 + if (cmd < 0)
1318 + return cmd;
1319 +
1320 + s_op.cmd_reg = cmd;
1321 +
1322 + if (op->cmd.opcode == SPINAND_PROGRAM_LOAD)
1323 + snandc->qspi->data_buf = (u8 *)op->data.buf.out;
1324 +
1325 + return 0;
1326 +}
1327 +
1328 +static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc,
1329 + const struct spi_mem_op *op)
1330 +{
1331 + struct qpic_snand_op s_op = {};
1332 + u32 cmd;
1333 + int ret, opcode;
1334 +
1335 + cmd = qcom_spi_cmd_mapping(snandc, op->cmd.opcode);
1336 + if (cmd < 0)
1337 + return cmd;
1338 +
1339 + s_op.cmd_reg = cmd;
1340 + s_op.addr1_reg = op->addr.val;
1341 + s_op.addr2_reg = 0;
1342 +
1343 + opcode = op->cmd.opcode;
1344 +
1345 + switch (opcode) {
1346 + case SPINAND_WRITE_EN:
1347 + return 0;
1348 + case SPINAND_PROGRAM_EXECUTE:
1349 + s_op.addr1_reg = op->addr.val << 16;
1350 + s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1351 + snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1352 + snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1353 + snandc->qspi->cmd = cpu_to_le32(cmd);
1354 + return qcom_spi_program_execute(snandc, op);
1355 + case SPINAND_READ:
1356 + s_op.addr1_reg = (op->addr.val << 16);
1357 + s_op.addr2_reg = op->addr.val >> 16 & 0xff;
1358 + snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg);
1359 + snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1360 + snandc->qspi->cmd = cpu_to_le32(cmd);
1361 + return 0;
1362 + case SPINAND_ERASE:
1363 + s_op.addr2_reg = (op->addr.val >> 16) & 0xffff;
1364 + s_op.addr1_reg = op->addr.val;
1365 + snandc->qspi->addr1 = cpu_to_le32(s_op.addr1_reg << 16);
1366 + snandc->qspi->addr2 = cpu_to_le32(s_op.addr2_reg);
1367 + snandc->qspi->cmd = cpu_to_le32(cmd);
1368 + qcom_spi_block_erase(snandc);
1369 + return 0;
1370 + default:
1371 + break;
1372 + }
1373 +
1374 + snandc->buf_count = 0;
1375 + snandc->buf_start = 0;
1376 + qcom_clear_read_regs(snandc);
1377 + qcom_clear_bam_transaction(snandc);
1378 +
1379 + snandc->regs->cmd = cpu_to_le32(s_op.cmd_reg);
1380 + snandc->regs->exec = cpu_to_le32(1);
1381 + snandc->regs->addr0 = cpu_to_le32(s_op.addr1_reg);
1382 + snandc->regs->addr1 = cpu_to_le32(s_op.addr2_reg);
1383 +
1384 + qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL);
1385 + qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL);
1386 +
1387 + ret = qcom_submit_descs(snandc);
1388 + if (ret)
1389 + dev_err(snandc->dev, "failure in submitting cmd descriptor\n");
1390 +
1391 + return ret;
1392 +}
1393 +
1394 +static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op)
1395 +{
1396 + int ret, val, opcode;
1397 + bool copy = false, copy_ftr = false;
1398 +
1399 + ret = qcom_spi_send_cmdaddr(snandc, op);
1400 + if (ret)
1401 + return ret;
1402 +
1403 + snandc->buf_count = 0;
1404 + snandc->buf_start = 0;
1405 + qcom_clear_read_regs(snandc);
1406 + qcom_clear_bam_transaction(snandc);
1407 + opcode = op->cmd.opcode;
1408 +
1409 + switch (opcode) {
1410 + case SPINAND_READID:
1411 + snandc->buf_count = 4;
1412 + qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL);
1413 + copy = true;
1414 + break;
1415 + case SPINAND_GET_FEATURE:
1416 + snandc->buf_count = 4;
1417 + qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1418 + copy_ftr = true;
1419 + break;
1420 + case SPINAND_SET_FEATURE:
1421 + snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out);
1422 + qcom_write_reg_dma(snandc, &snandc->regs->flash_feature,
1423 + NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL);
1424 + break;
1425 + case SPINAND_PROGRAM_EXECUTE:
1426 + case SPINAND_WRITE_EN:
1427 + case SPINAND_RESET:
1428 + case SPINAND_ERASE:
1429 + case SPINAND_READ:
1430 + return 0;
1431 + default:
1432 + return -EOPNOTSUPP;
1433 + }
1434 +
1435 + ret = qcom_submit_descs(snandc);
1436 + if (ret)
1437 + dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode);
1438 +
1439 + if (copy) {
1440 + qcom_nandc_dev_to_mem(snandc, true);
1441 + memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count);
1442 + }
1443 +
1444 + if (copy_ftr) {
1445 + qcom_nandc_dev_to_mem(snandc, true);
1446 + val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf);
1447 + val >>= 8;
1448 + memcpy(op->data.buf.in, &val, snandc->buf_count);
1449 + }
1450 +
1451 + return ret;
1452 +}
1453 +
1454 +static bool qcom_spi_is_page_op(const struct spi_mem_op *op)
1455 +{
1456 + if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4)
1457 + return false;
1458 +
1459 + if (op->data.dir == SPI_MEM_DATA_IN) {
1460 + if (op->addr.buswidth == 4 && op->data.buswidth == 4)
1461 + return true;
1462 +
1463 + if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1464 + return true;
1465 +
1466 + } else if (op->data.dir == SPI_MEM_DATA_OUT) {
1467 + if (op->data.buswidth == 4)
1468 + return true;
1469 + if (op->addr.nbytes == 2 && op->addr.buswidth == 1)
1470 + return true;
1471 + }
1472 +
1473 + return false;
1474 +}
1475 +
1476 +static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op)
1477 +{
1478 + if (!spi_mem_default_supports_op(mem, op))
1479 + return false;
1480 +
1481 + if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1)
1482 + return false;
1483 +
1484 + if (qcom_spi_is_page_op(op))
1485 + return true;
1486 +
1487 + return ((!op->addr.nbytes || op->addr.buswidth == 1) &&
1488 + (!op->dummy.nbytes || op->dummy.buswidth == 1) &&
1489 + (!op->data.nbytes || op->data.buswidth == 1));
1490 +}
1491 +
1492 +static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
1493 +{
1494 + struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller);
1495 +
1496 + dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode,
1497 + op->addr.val, op->addr.buswidth, op->addr.nbytes,
1498 + op->data.buswidth, op->data.nbytes);
1499 +
1500 + if (qcom_spi_is_page_op(op)) {
1501 + if (op->data.dir == SPI_MEM_DATA_IN)
1502 + return qcom_spi_read_page(snandc, op);
1503 + if (op->data.dir == SPI_MEM_DATA_OUT)
1504 + return qcom_spi_write_page(snandc, op);
1505 + } else {
1506 + return qcom_spi_io_op(snandc, op);
1507 + }
1508 +
1509 + return 0;
1510 +}
1511 +
1512 +static const struct spi_controller_mem_ops qcom_spi_mem_ops = {
1513 + .supports_op = qcom_spi_supports_op,
1514 + .exec_op = qcom_spi_exec_op,
1515 +};
1516 +
1517 +static const struct spi_controller_mem_caps qcom_spi_mem_caps = {
1518 + .ecc = true,
1519 +};
1520 +
1521 +static int qcom_spi_probe(struct platform_device *pdev)
1522 +{
1523 + struct device *dev = &pdev->dev;
1524 + struct spi_controller *ctlr;
1525 + struct qcom_nand_controller *snandc;
1526 + struct qpic_spi_nand *qspi;
1527 + struct qpic_ecc *ecc;
1528 + struct resource *res;
1529 + const void *dev_data;
1530 + int ret;
1531 +
1532 + ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
1533 + if (!ecc)
1534 + return -ENOMEM;
1535 +
1536 + qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL);
1537 + if (!qspi)
1538 + return -ENOMEM;
1539 +
1540 + ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false);
1541 + if (!ctlr)
1542 + return -ENOMEM;
1543 +
1544 + platform_set_drvdata(pdev, ctlr);
1545 +
1546 + snandc = spi_controller_get_devdata(ctlr);
1547 + qspi->snandc = snandc;
1548 +
1549 + snandc->dev = dev;
1550 + snandc->qspi = qspi;
1551 + snandc->qspi->ctlr = ctlr;
1552 + snandc->qspi->ecc = ecc;
1553 +
1554 + dev_data = of_device_get_match_data(dev);
1555 + if (!dev_data) {
1556 + dev_err(&pdev->dev, "failed to get device data\n");
1557 + return -ENODEV;
1558 + }
1559 +
1560 + snandc->props = dev_data;
1561 + snandc->dev = &pdev->dev;
1562 +
1563 + snandc->core_clk = devm_clk_get(dev, "core");
1564 + if (IS_ERR(snandc->core_clk))
1565 + return PTR_ERR(snandc->core_clk);
1566 +
1567 + snandc->aon_clk = devm_clk_get(dev, "aon");
1568 + if (IS_ERR(snandc->aon_clk))
1569 + return PTR_ERR(snandc->aon_clk);
1570 +
1571 + snandc->qspi->iomacro_clk = devm_clk_get(dev, "iom");
1572 + if (IS_ERR(snandc->qspi->iomacro_clk))
1573 + return PTR_ERR(snandc->qspi->iomacro_clk);
1574 +
1575 + snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1576 + if (IS_ERR(snandc->base))
1577 + return PTR_ERR(snandc->base);
1578 +
1579 + snandc->base_phys = res->start;
1580 + snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res),
1581 + DMA_BIDIRECTIONAL, 0);
1582 + if (dma_mapping_error(dev, snandc->base_dma))
1583 + return -ENXIO;
1584 +
1585 + ret = clk_prepare_enable(snandc->core_clk);
1586 + if (ret)
1587 + goto err_dis_core_clk;
1588 +
1589 + ret = clk_prepare_enable(snandc->aon_clk);
1590 + if (ret)
1591 + goto err_dis_aon_clk;
1592 +
1593 + ret = clk_prepare_enable(snandc->qspi->iomacro_clk);
1594 + if (ret)
1595 + goto err_dis_iom_clk;
1596 +
1597 + ret = qcom_nandc_alloc(snandc);
1598 + if (ret)
1599 + goto err_snand_alloc;
1600 +
1601 + ret = qcom_spi_init(snandc);
1602 + if (ret)
1603 + goto err_spi_init;
1604 +
1605 + /* setup ECC engine */
1606 + snandc->qspi->ecc_eng.dev = &pdev->dev;
1607 + snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED;
1608 + snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined;
1609 + snandc->qspi->ecc_eng.priv = snandc;
1610 +
1611 + ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng);
1612 + if (ret) {
1613 + dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret);
1614 + goto err_spi_init;
1615 + }
1616 +
1617 + ctlr->num_chipselect = QPIC_QSPI_NUM_CS;
1618 + ctlr->mem_ops = &qcom_spi_mem_ops;
1619 + ctlr->mem_caps = &qcom_spi_mem_caps;
1620 + ctlr->dev.of_node = pdev->dev.of_node;
1621 + ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL |
1622 + SPI_TX_QUAD | SPI_RX_QUAD;
1623 +
1624 + ret = spi_register_controller(ctlr);
1625 + if (ret) {
1626 + dev_err(&pdev->dev, "spi_register_controller failed.\n");
1627 + goto err_spi_init;
1628 + }
1629 +
1630 + return 0;
1631 +
1632 +err_spi_init:
1633 + qcom_nandc_unalloc(snandc);
1634 +err_snand_alloc:
1635 + clk_disable_unprepare(snandc->qspi->iomacro_clk);
1636 +err_dis_iom_clk:
1637 + clk_disable_unprepare(snandc->aon_clk);
1638 +err_dis_aon_clk:
1639 + clk_disable_unprepare(snandc->core_clk);
1640 +err_dis_core_clk:
1641 + dma_unmap_resource(dev, res->start, resource_size(res),
1642 + DMA_BIDIRECTIONAL, 0);
1643 + return ret;
1644 +}
1645 +
1646 +static void qcom_spi_remove(struct platform_device *pdev)
1647 +{
1648 + struct spi_controller *ctlr = platform_get_drvdata(pdev);
1649 + struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr);
1650 + struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1651 +
1652 + spi_unregister_controller(ctlr);
1653 +
1654 + qcom_nandc_unalloc(snandc);
1655 +
1656 + clk_disable_unprepare(snandc->aon_clk);
1657 + clk_disable_unprepare(snandc->core_clk);
1658 + clk_disable_unprepare(snandc->qspi->iomacro_clk);
1659 +
1660 + dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res),
1661 + DMA_BIDIRECTIONAL, 0);
1662 +}
1663 +
1664 +static const struct qcom_nandc_props ipq9574_snandc_props = {
1665 + .dev_cmd_reg_start = 0x7000,
1666 + .supports_bam = true,
1667 +};
1668 +
1669 +static const struct of_device_id qcom_snandc_of_match[] = {
1670 + {
1671 + .compatible = "qcom,spi-qpic-snand",
1672 + .data = &ipq9574_snandc_props,
1673 + },
1674 + {}
1675 +}
1676 +MODULE_DEVICE_TABLE(of, qcom_snandc_of_match);
1677 +
1678 +static struct platform_driver qcom_spi_driver = {
1679 + .driver = {
1680 + .name = "qcom_snand",
1681 + .of_match_table = qcom_snandc_of_match,
1682 + },
1683 + .probe = qcom_spi_probe,
1684 + .remove = qcom_spi_remove,
1685 +};
1686 +module_platform_driver(qcom_spi_driver);
1687 +
1688 +MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores");
1689 +MODULE_AUTHOR("Md Sadre Alam <quic_mdalam@quicinc.com>");
1690 +MODULE_LICENSE("GPL");
1691 +
1692 --- a/include/linux/mtd/nand-qpic-common.h
1693 +++ b/include/linux/mtd/nand-qpic-common.h
1694 @@ -325,6 +325,10 @@ struct nandc_regs {
1695 __le32 read_location_last1;
1696 __le32 read_location_last2;
1697 __le32 read_location_last3;
1698 + __le32 spi_cfg;
1699 + __le32 num_addr_cycle;
1700 + __le32 busy_wait_cnt;
1701 + __le32 flash_feature;
1702
1703 __le32 erased_cw_detect_cfg_clr;
1704 __le32 erased_cw_detect_cfg_set;
1705 @@ -339,6 +343,7 @@ struct nandc_regs {
1706 *
1707 * @core_clk: controller clock
1708 * @aon_clk: another controller clock
1709 + * @iomacro_clk: io macro clock
1710 *
1711 * @regs: a contiguous chunk of memory for DMA register
1712 * writes. contains the register values to be
1713 @@ -348,6 +353,7 @@ struct nandc_regs {
1714 * initialized via DT match data
1715 *
1716 * @controller: base controller structure
1717 + * @qspi: qpic spi structure
1718 * @host_list: list containing all the chips attached to the
1719 * controller
1720 *
1721 @@ -392,6 +398,7 @@ struct qcom_nand_controller {
1722 const struct qcom_nandc_props *props;
1723
1724 struct nand_controller *controller;
1725 + struct qpic_spi_nand *qspi;
1726 struct list_head host_list;
1727
1728 union {
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