8aaf117f58d1138d91c727e6c83ae2fdd3db819b
[openwrt/staging/ldir.git] /
1 From b36074357baf2794c825ea1c145de1d22b15380b Mon Sep 17 00:00:00 2001
2 From: Varadarajan Narayanan <quic_varada@quicinc.com>
3 Date: Fri, 20 Oct 2023 11:49:39 +0530
4 Subject: [PATCH] arm64: dts: qcom: ipq9574: populate the opp table based on
5 the eFuse
6
7 IPQ95xx SoCs have different OPPs available for the CPU based on
8 SoC variant. This can be determined from an eFuse register
9 present in the silicon.
10
11 Add support to read the eFuse and populate the OPPs based on it.
12
13 Frequency 1.2GHz 1.8GHz 1.5GHz No opp-supported-hw
14 Limit
15 ------------------------------------------------------------
16 936000000 1 1 1 1 0xf
17 1104000000 1 1 1 1 0xf
18 1200000000 1 1 1 1 0xf
19 1416000000 0 1 1 1 0x7
20 1488000000 0 1 1 1 0x7
21 1800000000 0 1 0 1 0x5
22 2208000000 0 0 0 1 0x1
23 -----------------------------------------------------------
24
25 Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
26 Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com>
27 Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
28 Link: https://lore.kernel.org/r/14ab08b7cfd904433ca6065fac798d4f221c9d95.1697781921.git.quic_varada@quicinc.com
29 Signed-off-by: Bjorn Andersson <andersson@kernel.org>
30 ---
31 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 21 ++++++++++++++++++++-
32 1 file changed, 20 insertions(+), 1 deletion(-)
33
34 diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
35 index 8a72ad4afd03..d4b7e215fc92 100644
36 --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
37 +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
38 @@ -106,42 +106,56 @@ memory@40000000 {
39 };
40
41 cpu_opp_table: opp-table-cpu {
42 - compatible = "operating-points-v2";
43 + compatible = "operating-points-v2-kryo-cpu";
44 opp-shared;
45 + nvmem-cells = <&cpu_speed_bin>;
46
47 opp-936000000 {
48 opp-hz = /bits/ 64 <936000000>;
49 opp-microvolt = <725000>;
50 + opp-supported-hw = <0xf>;
51 clock-latency-ns = <200000>;
52 };
53
54 opp-1104000000 {
55 opp-hz = /bits/ 64 <1104000000>;
56 opp-microvolt = <787500>;
57 + opp-supported-hw = <0xf>;
58 + clock-latency-ns = <200000>;
59 + };
60 +
61 + opp-1200000000 {
62 + opp-hz = /bits/ 64 <1200000000>;
63 + opp-microvolt = <862500>;
64 + opp-supported-hw = <0xf>;
65 clock-latency-ns = <200000>;
66 };
67
68 opp-1416000000 {
69 opp-hz = /bits/ 64 <1416000000>;
70 opp-microvolt = <862500>;
71 + opp-supported-hw = <0x7>;
72 clock-latency-ns = <200000>;
73 };
74
75 opp-1488000000 {
76 opp-hz = /bits/ 64 <1488000000>;
77 opp-microvolt = <925000>;
78 + opp-supported-hw = <0x7>;
79 clock-latency-ns = <200000>;
80 };
81
82 opp-1800000000 {
83 opp-hz = /bits/ 64 <1800000000>;
84 opp-microvolt = <987500>;
85 + opp-supported-hw = <0x5>;
86 clock-latency-ns = <200000>;
87 };
88
89 opp-2208000000 {
90 opp-hz = /bits/ 64 <2208000000>;
91 opp-microvolt = <1062500>;
92 + opp-supported-hw = <0x1>;
93 clock-latency-ns = <200000>;
94 };
95 };
96 @@ -223,6 +237,11 @@ qfprom: efuse@a4000 {
97 reg = <0x000a4000 0x5a1>;
98 #address-cells = <1>;
99 #size-cells = <1>;
100 +
101 + cpu_speed_bin: cpu-speed-bin@15 {
102 + reg = <0x15 0x2>;
103 + bits = <7 2>;
104 + };
105 };
106
107 cryptobam: dma-controller@704000 {
108 --
109 2.45.2
110