8aa498046dc1b8378e23e26fa2f347ce7aa8726d
[openwrt/staging/ansuel.git] /
1 From 492b06747f544c19b5ffe531a24b67858764c50e Mon Sep 17 00:00:00 2001
2 From: =?UTF-8?q?Alexis=20Lothor=C3=A9?= <alexis.lothore@bootlin.com>
3 Date: Mon, 29 May 2023 10:02:44 +0200
4 Subject: [PATCH 896/898] net: dsa: mv88e6xxx: fix 88E6393X family internal
5 phys layout
6 MIME-Version: 1.0
7 Content-Type: text/plain; charset=UTF-8
8 Content-Transfer-Encoding: 8bit
9
10 88E6393X/88E6193X/88E6191X switches have in fact 8 internal PHYs, but those
11 are not present starting at port 0: supported ports go from 1 to 8
12
13 Signed-off-by: Alexis Lothoré <alexis.lothore@bootlin.com>
14 Reviewed-by: Andrew Lunn <andrew@lunn.ch>
15 Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
16 Signed-off-by: Jakub Kicinski <kuba@kernel.org>
17 ---
18 drivers/net/dsa/mv88e6xxx/chip.c | 9 ++++++---
19 1 file changed, 6 insertions(+), 3 deletions(-)
20
21 --- a/drivers/net/dsa/mv88e6xxx/chip.c
22 +++ b/drivers/net/dsa/mv88e6xxx/chip.c
23 @@ -5372,7 +5372,8 @@ static const struct mv88e6xxx_info mv88e
24 .name = "Marvell 88E6191X",
25 .num_databases = 4096,
26 .num_ports = 11, /* 10 + Z80 */
27 - .num_internal_phys = 9,
28 + .num_internal_phys = 8,
29 + .internal_phys_offset = 1,
30 .max_vid = 8191,
31 .port_base_addr = 0x0,
32 .phy_base_addr = 0x0,
33 @@ -5394,7 +5395,8 @@ static const struct mv88e6xxx_info mv88e
34 .name = "Marvell 88E6193X",
35 .num_databases = 4096,
36 .num_ports = 11, /* 10 + Z80 */
37 - .num_internal_phys = 9,
38 + .num_internal_phys = 8,
39 + .internal_phys_offset = 1,
40 .max_vid = 8191,
41 .port_base_addr = 0x0,
42 .phy_base_addr = 0x0,
43 @@ -5704,7 +5706,8 @@ static const struct mv88e6xxx_info mv88e
44 .name = "Marvell 88E6393X",
45 .num_databases = 4096,
46 .num_ports = 11, /* 10 + Z80 */
47 - .num_internal_phys = 9,
48 + .num_internal_phys = 8,
49 + .internal_phys_offset = 1,
50 .max_vid = 8191,
51 .port_base_addr = 0x0,
52 .phy_base_addr = 0x0,