git.openwrt.org Git - openwrt/openwrt.git/blob

   1 From 5c4835e943dd31265770e7ca3c03307d5c725db6 Mon Sep 17 00:00:00 2001
   2 From: Viorel Suman <viorel.suman@nxp.com>
   3 Date: Thu, 25 Apr 2019 15:03:56 +0300
   4 Subject: [PATCH] MLK-21484-4: ASoC: fsl_sai: ensure clk not in use prior
   5  set_mclk_rate
   6
   7 On recent kernels clks which are marked with CLK_SET_RATE_GATE are
   8 "protected" against further changes at clk_prepare time, including clk
   9 set_parent and set_rate. See commit 9461f7b33d11 ("clk: fix
  10 CLK_SET_RATE_GATE with clock rate protection"). The current fsl_sai
  11 implementation ensures the clock is not in use prior set_parent,
  12 extend this for set_rate also by moving if (sai->mclk_streams == 0)
  13 outside fsl_sai_set_mclk_rate(). Aside of this avoid changing rate and
  14 parent for BUS clk.
  15
  16 Signed-off-by: Viorel Suman <viorel.suman@nxp.com>
  17 ---
  18  sound/soc/fsl/fsl_sai.c | 30 +++++++++++++-----------------
  19  1 file changed, 13 insertions(+), 17 deletions(-)
  20
  21 --- a/sound/soc/fsl/fsl_sai.c
  22 +++ b/sound/soc/fsl/fsl_sai.c
  23 @@ -259,25 +259,19 @@ static int fsl_sai_set_mclk_rate(struct
  24         if (pll) {
  25                 npll = (do_div(ratio, 8000) ? sai->pll11k_clk : sai->pll8k_clk);
  26                 if (!clk_is_match(pll, npll)) {
  27 -                       if (sai->mclk_streams == 0) {
  28 -                               ret = clk_set_parent(p, npll);
  29 -                               if (ret < 0)
  30 -                                       dev_warn(dai->dev,
  31 -                                               "failed to set parent %s: %d\n",
  32 -                                               __clk_get_name(npll), ret);
  33 -                       } else {
  34 -                               dev_err(dai->dev,
  35 -                                       "PLL %s is in use by a running stream.\n",
  36 -                                       __clk_get_name(pll));
  37 -                               return -EINVAL;
  38 -                       }
  39 +                       ret = clk_set_parent(p, npll);
  40 +                       if (ret < 0)
  41 +                               dev_warn(dai->dev,
  42 +                                        "failed to set parent %s: %d\n",
  43 +                                        __clk_get_name(npll), ret);
  44                 }
  45         }
  46
  47         ret = clk_set_rate(sai->mclk_clk[clk_id], freq);
  48         if (ret < 0)
  49                 dev_err(dai->dev, "failed to set clock rate (%u): %d\n",
  50 -                               freq, ret);
  51 +                       freq, ret);
  52 +
  53         return ret;
  54  }
  55
  56 @@ -298,7 +292,7 @@ static int fsl_sai_set_dai_sysclk(struct
  57         if (dir == SND_SOC_CLOCK_IN)
  58                 return 0;
  59
  60 -       if (freq > 0) {
  61 +       if (freq > 0 && clk_id != FSL_SAI_CLK_BUS) {
  62                 if (clk_id < 0 || clk_id >= FSL_SAI_MCLK_MAX) {
  63                         dev_err(cpu_dai->dev, "Unknown clock id: %d\n", clk_id);
  64                         return -EINVAL;
  65 @@ -309,9 +303,11 @@ static int fsl_sai_set_dai_sysclk(struct
  66                         return -EINVAL;
  67                 }
  68
  69 -               ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq);
  70 -               if (ret < 0)
  71 -                       return ret;
  72 +               if (sai->mclk_streams == 0) {
  73 +                       ret = fsl_sai_set_mclk_rate(cpu_dai, clk_id, freq);
  74 +                       if (ret < 0)
  75 +                               return ret;
  76 +               }
  77         }
  78
  79         ret = fsl_sai_set_dai_sysclk_tr(cpu_dai, clk_id, freq,